DS90UB964-Q1 Datasheet, PDF (31/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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GPIOx
Serializer
FPD-Link III
HUB Deserializer
BC_GPIOx
DS90UB964-Q1
SNLS500 – JULY 2016
GPIOx
Serializer
FPD-Link III
BC_GPIOx
GPIOx
Serializer
FPD-Link III
BC_GPIOx
GPIOx
Serializer
FPD-Link III
BC_GPIOx
GPIOy
Figure 27. External FrameSync
Enabling the external FrameSync mode is done by setting the FS_MODE control in the FS_CTL register to a
value between 0x8 (GPIO0 pin) to 0xF (GPIO7 pin). Set FS_GEN_ENABLE to 0 for this mode.
To send the FrameSync signal on a port’s BC_GPIOx signal, the BC_GPIO_CTL0 or BC_GPIO_CTL1 register
should be programmed for that port to select the FrameSync signal.
8.4.18.2 Internally Generated FrameSync
In Internal FrameSync mode, an internally generated FrameSync signal is sent to one or more of the attached
FPD3 Serializers via a GPIO signal in the back channel.
FrameSync operation is controlled by the FS_CTL 0x18, FS_HIGH_TIME_x, and FS_LOW_TIME_x 0x19–0x1A
registers. The resolution of the FrameSync generator clock (FS_CLK_PD) is derived from the back channel
frame period (BC_FREQ_SELECT register). For each 2.5 Mbps back-channel , the frame period is 12 µs (30 bits
* 400 ns/bit).
Once enabled, the FrameSync signal is sent continuously based on the programmed conditions.
Enabling the internal FrameSync mode is done by setting the FS_GEN_ENABLE control in the FS_CTL register
to a value of 1. The FS_MODE field controls the clock source used for the FrameSync generation. The
FS_GEN_MODE field configures whether the duty cycle of the FrameSync is 50/50 or whether the high and low
periods are controlled separately. The FrameSync high and low periods are controlled by the FS_HIGH_TIME
and FS_LOW_TIME registers.
The accuracy of the internally generated FrameSync is directly dependent on the accuracy of the 25 MHz
oscillator used as the reference clock.
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