DS90UB964-Q1 Datasheet, PDF (42/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
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WriteI2C(0x7c,0x01) # "FV_POLARITY"
WriteI2C(0x70,0x1f) # RAW10_datatype_yuv422b10_VC0
8.5.4 Interrupt Support
Interrupts can be brought out on the INTB pin as controlled by the INTERRUPT_CTL 0x23 and
INTERRUPT_STS 0x24 registers. The main interrupt control registers provide control and status for interrupts
from the individual sources. Sources include each of the four FPD3 Receive ports as well as each of the two
CSI-2 Transmit ports. Clearing interrupt conditions requires reading the associated status register for the source.
The setting of the individual interrupt status bits is not dependent on the related interrupt enable controls. The
interrupt enable controls whether an interrupt is generated based on the condition, but does not prevent the
interrupt status assertion.
For an interrupt to be generated based on one of the interrupt status assertions, both the individual interrupt
enable and the INT_EN control must be set in the INTERRUPT_CTL 0x23 register. For example, to generate an
interrupt if IS_RX0 is set, both the IE_RX0 and INT_EN bits must be set. If IE_RX0 is set but INT_EN is not, the
INT status is indicated in the INTERRUPT_STS register, and the INTB pin does not indicate the interrupt
condition.
See the INTERRUPT_CTL 0x23 and INTERRUPT_STS 0x24 register for details.
8.5.4.1 Code Example to Enable Interrupts
# "RX01/2/3/4 INTERRUPT_CTL enable"
WriteI2C(0x23,0xBF) # RX all & INTB PIN EN
# Individual RX01/2/3/4 INTERRUPT_CTL enable
# "RX0 INTERRUPT_CTL enable"
WriteI2C(0x4C,0x01) # RX0
WriteI2C(0x23,0x81) # RX0 & INTB PIN EN
# "RX1 INTERRUPT_CTL enable"
WriteI2C(0x4C,0x12) # RX1
WriteI2C(0x23,0x82) # RX1 & INTB PIN EN
# "RX2 INTERRUPT_CTL enable"
WriteI2C(0x4C,0x24) # RX2
WriteI2C(0x23,0x84) # RX2 & INTB PIN EN
# "RX3 INTERRUPT_CTL enable"
WriteI2C(0x4C,0x38) # RX3
WriteI2C(0x23,0x88) # RX3 & INTB PIN EN
8.5.4.2 FPD-Link III Receive Port Interrupts
For each FPD-Link III Receive port, multiple options are available for generating interrupts. Interrupt generation is
controlled via the PORT_ICR_HI 0xD8 and PORT_ICR_LO 0xD9 registers. In addition, the PORT_ISR_HI 0xDA
and PORT_ISR_LO 0xDB registers provide read-only status for the interrupts. Clearing of interrupt conditions is
handled by reading the RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS registers. The status bits in the
PORT_ISR_HI/LO registers are copies of the associated bits in the main status registers.
To enable interrupts from one of the Receive port interrupt sources:
1. Enable the interrupt source by setting the appropriate interrupt enable bit in the PORT_ICR_HI or
PORT_ICR_LO register
2. Set the RX Port X Interrupt control bit (IE_RXx) in the INTERRUPT_CTL register
3. Set the INT_EN bit in the INTERRUPT_CTL register to allow the interrupt to assert the INTB pin low
To clear interrupts from one of the Receive port interrupt sources:
1. (optional) Read the INTERRUPT_STS register to determine which RX Port caused the interrupt
2. (optional) Read the PORT_ISR_HI and PORT_ISR_LO registers to determine source of interrupt
3. Read the appropriate RX_PORT_STS1, RX_PORT_STS2, or CSI_RX_STS register to clear the interrupt.
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