DS90UB964-Q1 Datasheet, PDF (83/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Page Addr Register Name
(hex)
Share 0xB0 IND_ACC_CTL
Table 12. Serial Control Bus Registers (continued)
Bit(s) Field
Type Default Description
6
PASS_FREEZE
RW
0
Pass Freeze Control
This register controls whether the device will
include video freeze detection in qualification
of the Pass indication:
0 : Ignore video freeze detection
1 : Include video freeze detection
When enabled, Pass is deasserted upon
detection of a frozen image based on the
controls in the VIDEO_FREEZE register. Pass
will not be reasserted until a new video image
is detected and the PASS_THRESHOLD
setting is met.
5
PASS_LINE_CNT RW
0
Pass Line Count Control
This register controls whether the device will
include line count in qualification of the Pass
indication:
0 : Don't check line count
1 : Check line count
When checking line count, Pass is deasserted
upon detection of a change in the number of
video lines per frame. Pass will not be
reasserted until the PASS_THRESHOLD
setting is met.
4
PASS_LINE_SIZE RW
0
Pass Line Size Control
This register controls whether the device will
include line size in qualification of the Pass
indication: 0 : Don't check line size 1 : Check
line size When checking line size, Pass is
deasserted upon detection of a change in
video line size. Pass will not be reasserted until
the PASS_THRESHOLD setting is met.
3
PASS_PARITY_ERR RW
0
Parity Error Mode
If this bit is set to 0, the port Pass indication is
deasserted for every parity error detected on
the FPD3 Receive interface. If this bit is set to
a 1, the port Pass indication is cleared on a
parity error and remain clear until the
PASS_THRESHOLD is met.
2
PASS_WDOG_DIS RW
0
RX Port Pass Watchdog disable
When enabled, if the FPD Receiver does not
detect a valid frame end condition within two
video frame periods, the Pass indication is
deasserted. The watchdog timer will not have
any effect if the PASS_THRESHOLD is set to
0.
0 : Enable watchdog timer for RX Pass
1 : Disable watchdog timer for RX Pass
1:0 PASS_THRESHOLD RW
0x0
Pass Threshold Register
This register controls the number of valid
frames before asserting the port Pass
indication. If set to 0, PASS is asserted after
Receiver Lock detect. If non-zero, PASS is
asserted following reception of the
programmed number of valid frames.
7:6 RESERVED
R
0x0
Reserved
Copyright © 2016, Texas Instruments Incorporated
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