DS90UB964-Q1 Datasheet, PDF (24/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
8.4.6.1 Code Example for CMLOUT FPD3 RX Port 0:
WriteI2C(0xB0,0x14)
WriteI2C(0xB1,0x00)
WriteI2C(0xB2,0x80)
WriteI2C(0xB1,0x01)
WriteI2C(0xB2,0x01)
WriteI2C(0xB0,0x04)
WriteI2C(0xB1,0x0F)
WriteI2C(0xB2,0x01)
WriteI2C(0xB1,0x10)
WriteI2C(0xB2,0x02)
# FPD3 RX Shared, page 0
# Offset 0 (reg_0_sh)
# Enable loop throu driver
# Select Drive Mux
#
# FPD3 RX Port 0, page 0
#
# Loop through select
#
# Enable CML data output
8.4.7 GPIO Support
The DS90UB964-Q1 supports 8 pins which are programmable for use in multiple options through the
GPIOx_PIN_CTL registers.
8.4.7.1 Back Channel GPIO
The DS90UB964-Q1 can input data on the GPIO pins to send on the back channel to remote serializers. Each
GPIO pin can be programmed for input mode. In addition, the back channel for each FPD3 port can be
programmed to send any of the 8 GPIO pin data. The same GPIO pin can be connected to multiple back channel
GPIO signals.
In addition to sending GPIO from pins, an internally generated FrameSync signal may be sent on any of the
back-channel GPIOs.
For each port, the following GPIO control is available through the BC_GPIO_CTL0 register 0x6E and
BC_GPIO_CTL1 register 0x6F.
8.4.7.2 GPIO Pin Status
GPIO pin status may be read through the GPIO_PIN_STS register 0x0E. This register provides the status of the
GPIO pin independent of whether the GPIO pin is configured as an input or output.
8.4.7.3 Other GPIO Pin Controls
Each GPIO pin can has a input disable and a pulldown disable. By default, the GPIO pin input paths are enabled
and the internal pulldown circuit in the GPIO is enabled. The GPIO_INPUT_CTL register 0x0F and
GPIO_PD_CTL register 0xBE allow control of the input enable and the pulldown respectively. For most
applications, there is no need to modify the default register settings.
8.4.8 RAW Mode LV/FV Controls
The Raw modes provide FrameValid (FV) and LineValid (LV) controls for the video framing. The FV is equivalent
to a Vertical Sync (VSYNC) while the LineValid is equivalent to a Horizontal Sync (HSYNC) input to the
DS90UB913AQ/913Q/933Q device.
The DS90UB964-Q1 allows setting the polarity of these signals by register programming. The FV and LV polarity
are controlled on a per-port basis and can be independently set in the PORT_CONFIG2 register 0x7C.
To prevent false detection of FrameValid, FV must be asserted for a minimum number of clocks prior to first
video line to be considered valid. The minimum FrameValid time is programmable in the FV_MIN_TIME register
0xBC. Since the measurement is in FPD3 clocks, the minimum FrameValid setup to LineValid timing at the
Serializer will vary based on operating mode.
A minimum FV to LV timing is required when processing video frames at the serializer input. If the FV to LV
minimum setup is not met (by default), the first video line is discarded. Optionally, a register control
(PORT_CONFIG:DISCARD_1ST_ON_ERR) forwards the first video line missing some number of pixels at the
start of the line.
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