DS90UB964-Q1 Datasheet, PDF (35/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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WriteI2C(0x21,0x14) # Synchronized Basic_FWD
# "***FWD_PORT all RX to CSI0"
WriteI2C(0x20,0x00) # forwarding of all RX to CSI0
FS0 FS1 FS2 FS3
Line Blanking
FE0 FE1 FE2 FE3
C0L1
C1L1
C2L1
C3L1
.
.
.
.
.
.
C0LN
C1LN
C2LN
C3LN
Frame Blanking
Frame 1
Image Data
{Camera 0}
{Camera 1}
{Camera 2}
{Camera 3}
Frame Blanking
DS90UB964-Q1
SNLS500 – JULY 2016
KEY:
PH ± Packet Header
FS ± Frame Start
LS ± Line Start
Camera 0
VC-ID = 0
Camera 1
VC-ID = 1
PF ± Packet Footer + Filler (if applicable)
FE ± Frame End
LE ± Line End
Camera 2
VC-ID = 2
Camera 3
VC-ID = 3
*Blanking intervals do not provide accurate synchronization timing
Figure 30. Basic Synchronized Format
8.4.19.4 Line-Interleave Forwarding
In synchronized forwarding, the forwarding engine may be programmed to send only one of each synchronization
packet. For example, if forwarding from all four input ports, only one FS, FE packet is sent for each video frame.
The synchronization packets for the other 3 ports is dropped. The video line packets for each video stream are
sent as individual packets. This effectively merges the frames from N video sources into a single frame that has
N times the number of video lines.
In this mode, all video streams must also have the same VC, although this is not checked by the forwarding
engine. This is useful when connected to a controller that does not support multiple VCs. The receiving
processor must process the image based on order of video line reception.
Example Synchronized traffic to CSI-2 Transmit port at start of frame:
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