DS90UB964-Q1 Datasheet, PDF (48/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
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• Deassertion of Pass indication for an input port assigned to the CSI TX Port
• Loss of Synchronization between input video streams
• RX Port Interrupt – interrupts from RX Ports mapped to this CSI Transmit port
See the CSI_TX_ICR address 0x36 and CSI_TX_ISR address 0x37 registers for details.
The setting of the individual interrupt status bits is not dependent on the related interrupt enable controls. The
interrupt enable controls whether an interrupt is generated based on the condition, but does not prevent the
interrupt status assertion.
8.5.5 Timestamp – Video Skew Detection
The DS90UB964-Q1 implements logic to detect skew between video signaling from attached cameras. For each
input port, the DS90UB964-Q1 provides the ability to capture a time-stamp for both a start-of-frame and start-of-
line event. Comparison of timestamps can provide information on the relative skew between the ports. Start-of-
frame timestamps are generated at the active edge of the Vertical Sync signal in Raw mode. Start-of-line
timestamps are generated at the start of reception of the Nth line of video data after the start-of-frame for either
mode of operation. The function does not use the Line Start (LS) packet or Horizontal Sync controls to determine
the start of lines.
The skew detection can run in either a FrameSync mode or free-run mode.
Skew detection can be individually enabled for each RX port.
For start-of-line timestamps, a line number must be programmed. The same line number is used for all 4
channels. Prior to reading timestamps, the TS_FREEZE bit for each port that will be read should be set. This will
prevent overwrite of the timestamps by the detection circuit until all timestamps have been read. The freeze
condition will be released automatically once all frozen timestamps have been read. The freeze bits can also be
cleared if it does not read all the timestamp values.
The TS_STATUS register includes the following:
• Flags to indicate multiple start-of-frame per FrameSync period
• Flag to indicate Timestamps Ready
• Flags to indicate Timestamps valid (per port) – if ports are not synchronized, all ports may not indicate valid
timestamps
The Timestamp Ready flag will be cleared when the TS_FREEZE bit is cleared.
8.5.6 Pattern Generation
The DS90UB964-Q1 supports an internal pattern generation feature to provide a simple way to generate video
test patterns for the CSI-2 transmitter outputs. Two types of patterns are supported: Reference Color Bar pattern
and Fixed Color patterns.
The Pattern Generator is programmable with the following options:
• Number of color bars (1, 2, 4, or 8)
• Number of bytes per line
• Number of bytes per color bar
• CSI DataType field and VC-ID
• Number of active video lines per frame
• Number of total lines per frame (active plus blanking)
• Line period
• Vertical front porch – number of blank lines prior to FrameEnd packet
• Vertical back porch – number of blank lines following FrameStart packet
8.5.6.1 Code Example for Pattern Generator
#Patgen Fixed Colorbar 1280x720p30
WriteI2C(0x32,0x01) # CSI0 sel and CSI0 enable
WriteI2C(0x33,0x01)
WriteI2C(0xB0,0x00) # Indirect Pattern Gen Registers
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