DS90UB964-Q1 Datasheet, PDF (72/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr
(hex)
Share 0x42
Register Name
AEQ_CTL
Share 0x43 AEQ_ERR_THOLD
Share 0x4C FPD3_PORT_SEL
Bit(s) Field
7
RESERVED
6:4 AEQ_ERR_CTL
Type
R
3
RESERVED
RW
2
AEQ_2STEP_EN
RW
1
AEQ_OUTER_LOOP RW
0
AEQ_SFILTER_EN RW
7:0 AEQ_ERR_THRESH RW
OLD
7:6 PHYS_PORT_NUM R
Default Description
0
0x0
0
0
0
1
0x1
0x0
Port#
Reserved
AEQ Error Control
Setting any of these bits will enable FPD3 error
checking during the Adaptive Equalization
process. Errors are accumulated over 1/2 of
the period of the timer set by the
ADAPTIVE_EQ_RELOCK_TIME filed in the
AEQ_TEST register. If the number of errors is
greater than the programmed threshold
(AEQ_ERR_THOLD), the AEQ will attempt to
increase the EQ setting. The errors may also
be checked as part of EQ setting validation if
AEQ_2STEP_EN is set. The following errors
are checked based on this three bit field:
[2] FPD3 clk1/clk0 errors
[1] DCA sequence errors
[0] Parity errors
Reserved
AEQ 2-step enable
This bit enables a two-step operation as part of
the Adaptive EQ algorithm. If disabled, the
state machine will wait for a programmed
period of time, then check status to determine
if setting is valid. If enabled, the state machine
will wait for 1/2 the programmed period, then
check for errors over an additional 1/2 the
programmed period. If errors occur during the
2nd step, the state machine will immediately
move to the next setting.
0 : Wait for full programmed delay, then check
instantaneous lock value
1 : Wait for 1/2 programmed time, then check
for errors over 1/2 programmed time. The
programmed time is controlled by the
ADAPTIVE_EQ_RELOCK_TIME field in the
AEQ_TEST register
AEQ outer loop control
This bit controls whether the Equalizer or
SFILTER adaption is the outer loop when the
AEQ adaption includes SFILTER adaption.
0 : AEQ is inner loop, SFILTER is outer loop
1 : AEQ is outer loop, SFILTER is inner loop
Enable SFILTER Adaption with AEQ
Setting this bit allows SFILTER adaption as
part of the Adaptive Equalizer algorithm.
AEQ Error Threshold
This register controls the error threshold to
determine when to re-adapt the EQ settings.
This register should not be programmed to a
value of 0.
Physical port number
This field provides the physical port connection
when reading from a remote device via the Bi-
directional Control Channel.
When accessed via local I2C interfaces, the
value returned is always 0. When accessed via
Bi-directional Control Channel, the value
returned is the port number of the Receive port
connection.
72
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