DS90UB964-Q1 Datasheet, PDF (69/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

www.ti.com
DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
Bit(s) Field
4
TS_READY
Type
R
Share
Share
Share
Share
Share
Share
Share
Share
Share
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
3
2
1
0
TIMESTAMP_P0_HI 7:0
TIMESTAMP_P0_LO 7:0
TIMESTAMP_P1_HI 7:0
TIMESTAMP_P1_LO 7:0
TIMESTAMP_P2_HI 7:0
TIMESTAMP_P2_LO 7:0
TIMESTAMP_P3_HI 7:0
TIMESTAMP_P3_LO 7:0
CSI_PORT_SEL
7:5
4
TS_VALID3
R
TS_VALID2
R
TS_VALID1
R
TS_VALID0
R
TIMESTAMP_P0_HI R
TIMESTAMP_P0_LO R
TIMESTAMP_P1_HI R
TIMESTAMP_P1_LO R
TIMESTAMP_P2_HI R
TIMESTAMP_P2_LO R
TIMESTAMP_P3_HI R
TIMESTAMP_P3_LO R
RESERVED
R
TX_READ_PORT
RW
3:2 RESERVED
R
1
TX_WRITE_PORT_1 RW
0
TX_WRITE_PORT_0 RW
CSI 0x33 CSI_CTL
7
RESERVED
R
6
CSI_CAL_EN
RW
5:4 CSI_LANE_COUNT RW
Default Description
0
Timestamp Ready
This flag indicates when timestamps are ready
to be read. This flag is cleared when the
TS_FREEZE bit is set.
0
Timestamp Valid, RX Port 3
0
Timestamp Valid, RX Port 2
0
Timestamp Valid, RX Port 1
0
Timestamp Valid, RX Port 0
0x0
Timestamp, upper 8 bits, RX Port 0
0x0
Timestamp, lower 8 bits, RX Port 0
0x0
Timestamp, upper 8 bits, RX Port 1
0x0
Timestamp, lower 8 bits, RX Port 1
0x0
Timestamp, upper 8 bits, RX Port 2
0x0
Timestamp, lower 8 bits, RX Port 2
0x0
Timestamp, upper 8 bits, RX Port 3
0x0
Timestamp, lower 8 bits, RX Port 3
0x0
Reserved
0
Select TX port for register read
This field selects one of the two TX port
register blocks for readback. This applies to
the subsequent registers prefixed "CSI".
0: Port 0 registers
1: Port 1 registers
0x0
Reserved
0
Write Enable for TX port 1 registers
This bit enables writes to TX port 1 registers.
Any combination of TX port registers can be
written simultaneously. This applies to the
subsequent registers prefixed "CSI".
0: Writes disabled
1: Writes enabled
0
Write Enable for TX port 0 registers
This bit enables writes to TX port 0 registers.
Any combination of TX port registers can be
written simultaneously. This applies to the
subsequent registers prefixed "CSI".
0: Writes disabled
1: Writes enabled
0
Reserved
0
Enable initial CSI Skew-Calibration sequence
When the initial skew-calibration sequence is
enabled, the CSI Transmitter will send the
sequence at initialization, prior to sending any
HS data. This bit should be set when operating
at 1.6 Gbps CSI speed (as configured in the
CSI_PLL register).
0: Disabled
1: Enabled
0x0
CSI lane count
00: 4 lanes
01: 3 lanes
10: 2 lanes
11: 1 lane
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB964-Q1
Submit Documentation Feedback
69