DS90UB964-Q1 Datasheet, PDF (81/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
RX 0x72 RESERVED
RX 0x73 LINE_COUNT_1
RX 0x74 LINE_COUNT_0
RX 0x75 LINE_LEN_1
RX 0x76 LINE_LEN_0
RX 0x77 FREQ_DET_CTL
Bit(s) Field
Type Default Description
5:0 RAW12_DT
RW
7:0 Reserved
RW
7:0 LINE_COUNT_HI
R
7:0 LINE_COUNT_LO R
7:0 LINE_LEN_HI
R
7:0 LINE_LEN_LO
R
7:6 FREQ_HYST
RW
5:4 FREQ_STABLE_THR RW
0x2C
0x0
0x0
0x0
0
0
0x3
0x0
RAW12 DT
This field configures the CSI data type used in
RAW12 mode. The default of 0x2C matches
the CSI specification.
Reserved
High byte of Line Count
The Line Count reports the line count for the
most recent video frame. When interrupts are
enabled for the Line Count (via the
IE_LINE_CNT_CHG register bit), the Line
Count value is frozen until read.
Low byte of Line Count
The Line Count reports the line count for the
most recent video frame. When interrupts are
enabled for the Line Count (via the
IE_LINE_CNT_CHG register bit), the Line
Count value is frozen until read. In addition,
when reading the LINE_COUNT registers, the
LINE_COUNT_LO is latched upon reading
LINE_COUNT_HI to ensure consistency
between the two portions of the Line Count.
High byte of Line Length
The Line Length reports the line length
recorded during the most recent video frame. If
line length is not stable during the frame, this
register will report the length of the last line in
the video frame. When interrupts are enabled
for the Line Length (via the
IE_LINE_LEN_CHG register bit), the Line
Length value is frozen until read.
Low byte of Line Length
The Line Length reports the lenth of the most
recent video line. When interrupts are enabled
for the Line Length (via the
IE_LINE_LEN_CHG register bit), the Line
Length value is frozen until read. In addition,
when reading the LINE_LEN registers, the
LINE_LEN_LO is latched upon reading
LINE_LEN_HI to ensure consistency between
the two portions of the Line Length.
Frequency Detect Hysteresis
The Frequency detect hysteresis setting allows
ignoring minor fluctuations in frequency. A new
frequency measurement will be captured only if
the measured frequency differs from the
current measured frequency by more than the
FREQ_HYST setting. The FREQ_HYST
setting is in MHz.
Frequency Stable Threshold
The Frequency detect circuit can be used to
detect a stable clock frequency. The Stability
Threshold determines the amount of time
required for the clock frequency to stay within
the FREQ_HYST range to be considered
stable:
00 : 40us
01 : 80us
10 : 320us
11 : 1.28ms
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