DS90UB964-Q1 Datasheet, PDF (82/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
RX 0x78 MAILBOX_1
RX 0x79 MAILBOX_2
RX 0x7C PORT_CONFIG2
RX 0x7D PORT_PASS_CTL
Bit(s) Field
3:0 FREQ_LO_THR
Type
RW
7:0 MAILBOX_0
RW
7:0 MAILBOX_1
RW
7:6 RAW10_8BIT_CTL RW
5
DISCARD_ON_PAR_ RW
ERR
4
DISCARD_ON_LINE RW
_SIZE
3
DISCARD_ON_FRA RW
ME_SIZE
2
RESERVED
RW
1
LV_POLARITY
RW
0
FV_POLARITY
RW
7
PASS_DISCARD_EN RW
Default Description
0x5
0x0
0x01
0x0
0
0
0
0
0
0
0
Frequency Low Threshold
Sets the low threshold for the Clock frequency
detect circuit in MHz. This value is used to
determine if the clock frequency is too low for
proper operation.
Mailbox Register
This register is an unused read/write register
that can be used for any purpose such as
passing messages between I2C masters on
opposite ends of the link.
Mailbox Register
This register is an unused read/write register
that can be used for any purpose such as
passing messages between I2C masters on
opposite ends of the link.
Raw10 8-bit mode
When Raw10 Mode is enabled for the port, the
input data is processed as 8-bit data and
packed accordingly for transmission over CSI.
00 : Normal Raw10 Mode
01 : Reserved
10 : 8-bit processing using upper 8 bits
11 : 8-bit processing using lower 8 bits
Discard frames on Parity Error
0 : Forward packets with parity errors
1 : Truncate Frames if a parity error is detected
Discard frames on Line Size
0 : Allow changes in Line Size within packets
1 : Truncate Frames if a change in line size is
detected
Discard frames on change in Frame Size
When enabled, a change in the number of
lines in a frame will result in truncation of the
packet. The device will resume forwarding
video frames based on the
PASS_THRESHOLD setting in the
PORT_PASS_CTL register.
0 : Allow changes in Frame Size
1 : Truncate Frames if a change in frame size
is detected
Reserved
LineValid Polarity
This register indicates the expected polarity for
the LineValid indication received in Raw mode.
1 : LineValid is low for the duration of the video
frame
0 : LineValid is high for the duration of the
video frame
FrameValid Polarity
This register indicates the expected polarity for
the FrameValid indication received in Raw
mode.
1 : FrameValid is low for the duration of the
video frame
0 : FrameValid is high for the duration of the
video frame
Pass Discard Enable
Discard packets if PASS is not indicated.
0 : Ignore PASS for forwarding packets
1 : Discard packets when PASS is not true
82
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