DS90UB964-Q1 Datasheet, PDF (50/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
8.6 Register Description
The DS90UB964-Q1 implements the following register blocks, accessible via I2C as well as the bi-directional
control channel:
• Main Registers
• FPD3 RX Port Registers (separate register block for each of the four RX ports)
• CSI-2 Port Registers (separate register block for each of the CSI-2 ports)
ADDRESS
RANGE
0x00-0x31
0x32-0x3A
0x4C-0x7F
0x80-0x9F
0xA0-0xAF
0xB0-0xB2
0xB0-0xBF
0xC0-0xCF
0xD0-0xDF
0xE0-0xEF
0xF0-0xF5
0xF8-0xFB
0xF6-0xF7
0xFC-0xFF
Table 11. Main Register Map Descriptions
DESCRIPTION
Digital Shared Registers
Digital CSI-2 Registers
(paged, broadcast write allowed)
Digital RX Port Registers
(paged, broadcast write allowed)
Reserved
Reserved
Indirect Access Registers
Digital Share Registers
Reserved
Digital RX Port Debug Registers
Reserved
FPD3 RX ID
Port I2C Addressing
Reserved
CSI-2 TX Port 0
R: 0x32[4]=0
W: 0x32[0]=1
FPD3 RX Port 0
R: 0x4C[5:4]=00
W: 0x4C[0]=1
FPD3 RX Port 0
ADDRESS MAP
Shared
CSI-2 TX Port 1
R: 0x32[4]=1
W: 0x32[1]=1
FPD3 RX Port 1
R: 0x4C[5:4]=01
W: 0x4C[1]=1
FPD3 RX Port 2
R: 0x4C[5:4]=10
W: 0x4C[2]=1
Reserved
Reserved
Shared
Shared
Reserved
FPD3 RX Port 1 FPD3 RX Port 2
Reserved
Shared
Shared
Reserved
FPD3 RX Port 3
R: 0x4C[5:4]=11
W: 0x4C[3]=1
FPD3 RX Port 3
LEGEND:
• RW = Read Write
• RW/SC = RW/SC = Read Write access/Self Clearing bit
• R = Read Only, Permanent value
• R/COR = Read Only, Clear On Read
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