DS90UB964-Q1 Datasheet, PDF (63/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr
(hex)
Share 0x18
Register Name
FS_CTL
Share 0x19 FS_HIGH_TIME_1
Share 0x1A FS_HIGH_TIME_0
Bit(s) Field
Type Default Description
7:4 FS_MODE
RW
0x0
3
FS_SINGLE
RW/SC 0
2
FS_INIT_STATE
RW
0
1
FS_GEN_MODE
RW
0
0
FS_GEN_ENABLE RW
0
7:0 FRAMESYNC_HIGH RW
0x0
_TIME_1
7:0 FRAMESYNC_HIGH RW
0x0
_TIME_0
FrameSync Mode
0000: Internal Generated FrameSync, use
Back-channel frame clock from port 0
0001: Internal Generated FrameSync, use
Back-channel frame clock from port 1
0010: Internal Generated FrameSync, use
Back-channel frame clock from port 2
0011: Internal Generated FrameSync, use
Back-channel frame clock from port 3
01xx: Internal Generated FrameSync, use
25MHz clock
1000: External FrameSync from GPIO0
1001: External FrameSync from GPIO1
1010: External FrameSync from GPIO2
1011: External FrameSync from GPIO3
1100: External FrameSync from GPIO4
1101: External FrameSync from GPIO5
1110: External FrameSync from GPIO6
1111: External FrameSync from GPIO7
Generate Single FrameSync pulse
When this bit is set, a single FrameSync pulse
is generated. The system should wait for the
full duration of the desired pulse before
generating another pulse. When using this
feature, the FS_GEN_ENABLE bit should
remain set to 0. This bit is self-clearing and will
always return 0.
Initial State
This register controls the initial state of the
FrameSync signal.
0: FrameSync initial state is 0
1: FrameSync initial state is 1
FrameSync Generation Mode
This control selects between Hi/Lo and 50/50
modes. In Hi/Lo mode, the FrameSync
generator will use the FS_HIGH_TIME and
FS_LOW_TIME register values to separately
control the High and Low periods for the
generated FrameSync signal. In 50/50 mode,
the FrameSync generator will use the values in
the FS_HIGH_TIME_0, FS_LOW_TIME_1 and
FS_LOW_TIME_0 registers as a 24-bit value
for both the High and Low periods of the
generated FrameSync signal.
0: Hi/Lo
1: 50/50
FrameSync Generation Enable
0: Disabled
1: Enabled
FrameSync High Time bits 15:8
The value programmed to the FS_HIGH_TIME
register should be reduced by 1 from the
desired delay. For example, a value of 0 in the
FRAMESYNC_HIGH_TIME field will result in a
1 cycle high pulse on the FrameSync signal.
FrameSync High Time bits 7:0
The value programmed to the FS_HIGH_TIME
register should be reduced by 1 from the
desired delay. For example, a value of 0 in the
FRAMESYNC_HIGH_TIME field will result in a
1 cycle high pulse on the FrameSync signal.
Copyright © 2016, Texas Instruments Incorporated
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