DS90UB964-Q1 Datasheet, PDF (53/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Page Addr
(hex)
Share 0x09
Share 0x0A
Share 0x0B
Share 0x0C
Register Name
I2C Control 2
SCL High Time
SCL Low Time
RX_PORT_CTL
Table 12. Serial Control Bus Registers (continued)
Bit(s) Field
Type Default Description
7:4 SDA Output Setup RW
3:2 SDA Output Delay RW
1
I2C BUS TIMER
RW
SPEEDUP
0
I2C BUS TIMER
RW
DISABLE
7:0 SCL HIGH TIME
RW
7:0 SCL LOW TIME
RW
7
BCC3_MAP
RW
6
BCC2_MAP
RW
0x1
0x0
0
0
0x79
0x79
0
0
Remote Ack SDA Output Setup
When a Control Channel (remote) access is
active, this field configures setup time from the
SDA output relative to the rising edge of SCL
during ACK cycles. Setting this value will
increase setup time in units of 640ns. The
nominal output setup time value for SDA to
SCL when this field is 0 is 80ns.
SDA Output Delay
This field configures additional delay on the
SDA output relative to the falling edge of SCL.
Setting this value will increase output delay in
units of 40ns. Nominal output delay values for
SCL to SDA are:
00: 240ns
01: 280ns
10: 320ns
11: 360ns
Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately
50 microseconds
0: Watchdog Timer expires after approximately
1 second.
Disable I2C Bus Watchdog Timer
When the I2C Watchdog Timer may be used to
detect when the I2C bus is free or hung up
following an invalid termination of a
transaction. If SDA is high and no signalling
occurs for approximately 1 second, the I2C bus
will assumed to be free. If SDA is low and no
signaling occurs, the device will attempt to
clear the bus by driving 9 clocks on SCL
I2C Master SCL High Time
This field configures the high pulse width of the
SCL output when the Serializer is the Master
on the local I2C bus. Units are 40 ns for the
nominal oscillator clock frequency. The default
value is set to provide a minimum 5us SCL
high time with the reference clock at 25 MHz +
100ppm. The delay includes 5 additional
oscillator clock periods.
Min_delay = 39.996ns * (SCL_HIGH_TIME +
5)
I2C SCL Low Time
This field configures the low pulse width of the
SCL output when the Serializer is the Master
on the local I2C bus. This value is also used as
the SDA setup time by the I2C Slave for
providing data prior to releasing SCL during
accesses over the Bi-directional Control
Channel. Units are 40 ns for the nominal
oscillator clock frequency. The default value is
set to provide a minimum 5us SCL low time
with the reference clock at 25 MHz + 100ppm.
The delay includes 5 additional clock periods.
Min_delay = 39.996ns * (SCL_LOW_TIME+ 5)
Map Control Channel 3 to I2C Slave Port
0: I2C Slave Port 0
1: I2C Slave Port 1
Map Control Channel 2 to I2C Slave Port
0: I2C Slave Port 0
1: I2C Slave Port 1
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