DS90UB964-Q1 Datasheet, PDF (15/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN OR
FREQUENCY
t_HS-SKIP
Time interval during which the
HS-RX should ignore any
transitions on the Data Lane,
following a HS burst. The end
point of the interval is defined
as the beginning of the LP-11
state following the HS burst.⁽¹⁾
t_HS-TRAIL
Data Lane HS Exit⁽¹⁾
t_LPX
t_WAKEUP
Transmitted length of LP
state ⁽¹⁾
Recovery Time from Ultra Low
Power State (ULPS)⁽¹⁾
MIN
40
60 +
4×UI_INS
T
50
1
t_CLH
80%
20%
t_CHL
V_DDIO
GND
Figure 1. LVCMOS Transition Times
DS90UB964-Q1
SNLS500 – JULY 2016
TYP MAX UNIT
55 +
4×UI_INS ns
T
ns
ns
ms
V+
VCM
VID
V-
GND
Figure 2. FPD-Link III Receiver VID
PDB=H
R_IN±
t_DDLT
GPIOx
(LOCK)
VDDIO/2
Figure 3. Deserializer Data Lock Time
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