DS90UB964-Q1 Datasheet, PDF (89/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

www.ti.com
DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Page Addr Register Name
(hex)
Share
Share
Share
Share
Share
Share
Share
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF8
FPD3_RX_ID0
FPD3_RX_ID1
FPD3_RX_ID2
FPD3_RX_ID3
FPD3_RX_ID4
FPD3_RX_ID5
I2C_RX0_ID
Table 12. Serial Control Bus Registers (continued)
Bit(s) Field
Type Default Description
6
IS_LINE_LEN_CHG R
5
IS_LINE_CNT_CHG R
4
IS_BUFFER_ERR R
3
RESERVED
R
2
IS_FPD3_PAR_ERR R
1
IS_PORT_PASS
R
0
IS_LOCK_STS
R
7:0 FPD3_RX_ID0
R
7:0 FPD3_RX_ID1
R
7:0 FPD3_RX_ID2
R
7:0 FPD3_RX_ID3
R
7:0 FPD3_RX_ID4
R
7:0 FPD3_RX_ID5
R
7:1 RX_PORT0_ID
RW
0
RESERVED
R
0
0
0
0
0
0
0
0x5F
0x55
0x42
0x39
0x36
0x34
0x0
0
Video Line Length Interrupt Status
A change in video line length has been
detected. Status is reported in the
LINE_LEN_CHG bit in the RX_PORT_STS2
register.
This interrupt condition is cleared by reading
the RX_PORT_STS2 register.
Video Line Count Interrupt Status
A change in number of video lines per frame
has been detected. Status is reported in the
LINE_CNT_CHG bit in the RX_PORT_STS2
register.
This interrupt condition is cleared by reading
the RX_PORT_STS2 register.
Receiver Buffer Error Interrupt Status
A Receive Buffer overflow has been detected
as reported in the BUFFER_ERROR bit in the
RX_PORT_STS2 register.This interrupt
condition is cleared by reading the
RX_PORT_STS2 register.
Reserved
FPD-Link III Receiver Parity Error Interrupt
Status
A parity error on the FPD-Link III interface for
the receive port has been detected. Parity error
status is reported in the PARITY_ERROR bit in
the RX_PORT_STS1 register.
This interrupt condition is cleared by reading
the RX_PORT_STS1 register.
Port Valid Interrupt Status
A change in receiver port valid status as
reported in the PORT_PASS bit in the
PORT_STS1 register. This interrupt condition
is cleared by reading the RX_PORT_STS1
register.
Lock Interrupt Status
A change in lock status has been detected.
Status is reported in the LOCK_STS_CHG bit
in the RX_PORT_STS1 register.
This interrupt condition is cleared by reading
the RX_PORT_STS1 register.
FPD3_RX_ID0: First byte ID code: ‘_’
FPD3_RX_ID1: 2nd byte of ID code: ‘U’
FPD3_RX_ID2: 3rd byte of ID code: ‘B’
FPD3_RX_ID3: 4th byte of ID code: ‘9’
FPD3_RX_ID4: 5th byte of ID code: '6'
FPD3_RX_ID5: 6th byte of ID code: '4'
7-bit Receive Port 0 I2C ID
Configures the decoder for detecting
transactions designated for Receiver port 0
registers. This provides a simpler method of
accessing device registers specifically for port
0 without having to use the paging function to
select the register page. A value of 0 in this
field disables the Port0 decoder.
Reserved
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB964-Q1
Submit Documentation Feedback
89