DS90UB964-Q1 Datasheet, PDF (23/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
8.4.5 Adaptive Equalizer
The receiver inputs provide an adaptive equalization filter in order to compensate for signal degradation from the
interconnect components. In order to determine the maximum cable reach, factors that affect signal integrity such
as jitter, skew, ISI, crosstalk, etc. need to be taken into consideration. The equalization status and configuration
are selected via AEQ registers 0xD2–0xD5.
Each RX receiver incorporates an adaptive equalizer (AEQ), which continuously monitors cable characteristics
for long-term cable aging and temperature changes. The AEQ attempts to optimize the equalization setting of the
RX receiver.
If the deserializer loses LOCK, the adaptive equalizer will reset and perform the LOCK algorithm again to
reacquire the serial data stream being sent by the serializer.
8.4.6 Channel Monitor Loop-Through Output Driver
The DS90UB964-Q1 includes an internal Channel Monitor Loop-through output on the CMLOUTP/N pins. A
buffered loop-through output driver is provided on the CMLOUTP/N for observing jitter after equalization for each
of the four RX receive channels. The CMLOUT monitors the post EQ stage thus providing the recovered input of
the deserializer signal. The measured serial data width on the CMLOUT loop-through is the total jitter including
the internal driver, AEQ, back channel echo, etc. Each channel also has its own CMLOUT monitor and can be
used for debug purposes. This CMLOUT is useful in identifying gross signal conditioning issues.
Table 6 includes details on selecting the corresponding RX receiver of CMLOUTP/N configuration.
Table 5. CML Monitor Output Driver
PARAMETER
E_W
Differential Output Eye
Opening
TEST CONDITIONS
R_L = 100 Ω
(Figure 16)
PIN
CMLOUTP,
CMLOUTN
MIN
0.45
TYP
MAX UNIT
UI ⁽¹⁾
(1) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with serializer input PCLK frequency.
10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 x 28 )
12-bit HF mode: 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 )
12-bit LF mode: 1 UI = 1 / ( PCLK_Freq. x 28 )
Ew
t_BIT (1 UI)
VOD (+)
0V
VOD (-)
Figure 16. CMLOUT Output Driver
Table 6. Channel Monitor Loop-Through Output Configuration
ENABLE MAIN LOOPTHRU DRIVER
SELECT CHANNEL MUX
SELECT RX PORT
FPD3 RX Port 0
0xB0 = 0x14
0xB1 = 0x00
0xB2 = 0x80
0xB1 = 0x01
0xB2 = 0x01
0xB0 = 0x04
0xB1 = 0x0F
0xB2 = 0x01
0xB1 = 0x10
0xB2 = 0x02
FPD3 RX Port 1
0xB0 = 0x14
0xB1 = 0x00
0xB2 = 0x80
0xB1 = 0x01
0xB2 = 0x02
0xB0 = 0x08
0xB1 = 0x0F
0xB2 = 0x01
0xB1 = 0x10
0xB2 = 0x02
FPD3 RX Port 2
0xB0 = 0x14
0xB1 = 0x00
0xB2 = 0x80
0xB1 = 0x01
0xB2 = 0x04
0xB0 = 0x0C
0xB1 = 0x0F
0xB2 = 0x01
0xB1 = 0x10
0xB2 = 0x02
FPD3 RX Port 3
0xB0 = 0x14
0xB1 = 0x00
0xB2 = 0x80
0xB1 = 0x01
0xB2 = 0x08
0xB0 = 0x10
0xB1 = 0x0F
0xB2 = 0x01
0xB1 = 0x10
0xB2 = 0x02
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