DS90UB964-Q1 Datasheet, PDF (106/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
11.2 Layout Example
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the VQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP.
Example PCB layout is used to demonstrate both proper routing and proper solder techniques when designing in
the Deserializer.
RIN0+/-
RIN1+/-
RIN2+/-
RIN3+/-
CSI0_D3P/N
CSI0_D2P/N
CSI0_D1P/N
CSI0_D0P/N
CSI0_CLKP/N
Figure 46. Simplified Layout Example
Figure 47 shows a PCB layout example are derived from the layout design of the DS90UB96X-Q1EVM
Evaluation Board. The graphic and layout description are used to determine proper routing when designing the
board. The high speed FPD-Link III traces routed differentially up to the connector. A 100Ω differential
characteristic impedance and 50Ω single-ended characteristic impedance traces are maintained as much as
possible for both STP and coaxial applications. For the layout of a coaxial interconnects, coupled traces should
be used with the RINx- termination near to the connector.
Figure 47. DS90UB964-Q1 Example PCB Layout
106 Submit Documentation Feedback
Product Folder Links: DS90UB964-Q1
Copyright © 2016, Texas Instruments Incorporated