DS90UB964-Q1 Datasheet, PDF (17/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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Clock Lane
DS90UB964-Q1
SNLS500 – JULY 2016
Data Lane
Dp/Dn
VOH
VIH(min)
VIL(max)
T_LPX
T_HS-ZERO
THS-PREPARE
VOL
LP-11
T_D-TERM-EN
LP-01
LP-00
T_HS-SETTLE
T_HS-SYNC
Capture
1^st Data Bit
LOW POWER TO
HIGH SPEED
TRANSITION
HS-ZERO
START OF
TRANSMISSION
SEQUENCE
HIGH SPEED DATA
TRANSMISSION
Figure 6. High Speed Data Transmission Burst
Clock Lane
Dp/Dn
T_CLK-POST
VIH(min)
VIL(max)
T_EOT
T_CLK-MISS
Disconnect
Terminator
T_CLK-SETTLE
TCLK-TERM-EN
Disconnect
Terminator
T_REOT
T_HS-SKIP LP-11
T_EOT
T_HS-TRAIL
T_HS-EXIT
HS-TRAIL
HIGH SPEED
TO
LOW POWER
TRANSITION
T_CLK-TRAIL
Data Lane
Dp/Dn
Disconnect
Terminator
T_HS-EXIT
T_LPX
T_CLK-ZERO
T_CLK-PREPARE
T_CLK-PRE
T_LPX
T_HS-PREPARE
VIH(min)
VIL(max)
T_HS-SKIP
T_D-TERM-EN
T_HS-SETTLE
Figure 7. Switching the Clock Lane between Clock Transmission and Low-Power Mode
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