DS90UB964-Q1 Datasheet, PDF (40/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
Programming (continued)
Table 10. Serial Control Bus Addresses for IDx
NO.
TARGET VOLTAGE
V_R1 min (V)
V_R1 typ (V)
V_R1 max (V)
SUGGESTED R1 SUGGESTED R2
kΩ (1% tol)
kΩ (1% tol)
0
0
0
0.237
OPEN
40.2
1
0.293
0.367
0.440
118
30.9
2
0.507
0.579
0.650
107
51.1
3
0.716
0.783
0.849
113
88.7
4
0.924
0.992
1.059
82.5
102
5
1.139
1.205
1.271
68.1
137
6
1.350
1.416
1.481
56.2
210
7
1.561
VDD18
VDD18
13.3
OPEN
7-BIT
ADDRESS
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3D
8-BIT
ADDRESS
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7A
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 34 .
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 34. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it acknowledges (ACKs) the master by driving the SDA bus low. If the address does not
match a device's slave address, it not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 35 and a WRITE is shown in Figure 36.
N
Bus Activity:
A
Master
Slave
Register
Slave
C
Address
Address
Address
K
SDA Line S
7-bit Address 0
S
7-bit Address 1
P
Bus Activity:
Slave
A
A
C
C
K
K
A
Data
C
K
Figure 35. Serial Control Bus — READ
40
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