DS90UB964-Q1 Datasheet, PDF (51/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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8.7 Register Maps
Page Addr
(hex)
Share 0x00
Register Name
I2C_DEVICE_ID
Share 0x01 RESET_CTL
Share 0x02 GENERAL_CFG
DS90UB964-Q1
SNLS500 – JULY 2016
Table 12. Serial Control Bus Registers
Bit(s) Field
Type Default Description
7:1 DEVICE_ID
RW
Strap 7-bit I2C ID of Deserializer.
This field always indicates the current value of
the I2C ID. When bit 0 of this register is 0, this
field is read-only and show the strapped ID.
When bit 0 of this register is 1, this field is
read/write and can be used to assign any valid
I2C ID.
0
DES_ID
RW
0
0: Device ID is from strap
1: Register I2C Device ID overrides strapped
value
7:6 RESERVED
R
0x0
Reserved
5
RESERVED
RW
0
Reserved
4:3 RESERVED
R
0x0
Reserved
2
RESTART_AUTOLO RW/SC 0
AD
Restart ROM Auto-load
Setting this bit to 1 causes a re-load of the
ROM. This bit is self-clearing. Software may
check for Auto-load complete by checking the
CFG_INIT_DONE bit in the DEVICE_STS
register.
1
DIGITAL RESET1 RW/SC 0
Digital Reset
Resets the entire digital block including
registers. This bit is self-clearing.
1: Reset
0: Normal operation
0
DIGITAL RESET0 RW/SC 0
Digital Reset
Resets the entire digital block except registers.
This bit is self-clearing.
1: Reset
0: Normal operation
7:5 RESERVED
R
0x0
Reserved
4
OUTPUT_EN_MODE RW
1
Output Enable Mode
If set to 0, the CSI TX output port is forced to
the high-impedance state if no assigned RX
ports have an active Receiver lock.
If set to 1, the CSI TX output port will continue
in normal operation if no assigned RX ports
have an active Receiver lock. CSI TX
operation will remain under register control via
the CSI_CTL register for each port. If no
assigned RX ports have an active Receiver
lock, this will result in the CSI Transmitter
entering the LP-11 state.
3
OUTPUT_ENABLE RW
1
Output Enable Control (in conjunction with
Output Sleep State Select)
If OUTPUT_SLEEP_STATE_SEL is set to 1
and this bit is set to 0, the CSI TX outputs is
forced into a high impedance state.
2
OUTPUT_SLEEP_ST RW
1
ATE_SEL
OSS Select to control output state when LOCK
is low (used in conjunction with Output Enable)
When this bit is set to 0, the CSI TX outputs is
forced into a HS-0 state.
1
RX_PARITY_CHECK RW
1
ER_EN
FPD3 Receiver Parity Checker Enable When
enabled, the parity check function is enabled
for the FPD3 receiver. This allows detection of
errors on the FPD3 receiver data bits.
0: Disable
1: Enable
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