DS90UB964-Q1 Datasheet, PDF (67/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
Share 0x24 INTERRUPT_STS
Bit(s) Field
6
RESERVED
5
IE_CSI_TX1
4
IE_CSI_TX0
3
IE_RX3
2
IE_RX2
1
IE_RX1
0
IE_RX0
7
INT
6
RESERVED
5
IS_CSI_TX1
4
IS_CSI_TX0
3
IS_RX3
2
IS_RX2
1
IS_RX1
0
IS_RX0
Type Default Description
R
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Reserved
CSI Transmit Port 1 Interrupt:
Enable interrupt from CSI Transmitter Port 1.
CSI Transmit Port 1 Interrupt:
Enable interrupt from CSI Transmitter Port 0.
RX Port 3 Interrupt:
Enable interrupt from Receiver Port 3.
RX Port 2 Interrupt:
Enable interrupt from Receiver Port 2.
RX Port 1 Interrupt:
Enable interrupt from Receiver Port 1.
RX Port 0 Interrupt:
Enable interrupt from Receiver Port 0.
Global Interrupt:
Set if any enabled interrupt is indicated in the
individual status bits in this register. The
setting of this bit is not dependent on the
INT_EN bit in the INTERRUPT_CTL register
but does depend on the IE_xxx bits. For
example, if IE_RX0 and IS_RX0 are both
asserted, the INT bit is set to 1.
Reserved
CSI Transmit Port 1 Interrupt:
An interrupt has occurred for CSI Transmitter
Port 1. This interrupt is cleared upon reading
the CSI_TX_ISR register for CSI Transmit Port
1.
CSI Transmit Port 0 Interrupt:
An interrupt has occurred for CSI Transmitter
Port 0. This interrupt is cleared upon reading
the CSI_TX_ISR register for CSI Transmit Port
0.
RX Port 3 Interrupt:
This interrupt is cleared by reading the
associated status register(s) for the event(s)
that caused the interrupt. The status registers
are RX_PORT_STS1, RX_PORT_STS2, and
CSI_RX_STS.
RX Port 2 Interrupt:
An interrupt has occurred for Receive Port 2.
This interrupt is cleared by reading the
associated status register(s) for the event(s)
that caused the interrupt. The status registers
are RX_PORT_STS1, RX_PORT_STS2, and
CSI_RX_STS.
RX Port 1 Interrupt:
0x An interrupt has occurred for Receive Port
1. This interrupt is cleared by reading the
associated status register(s) for the event(s)
that caused the interrupt. The status registers
are RX_PORT_STS1, RX_PORT_STS2, and
CSI_RX_STS.
RX Port 0 Interrupt:
An interrupt has occurred for Receive Port 0.
This interrupt is cleared by reading the
associated status register(s) for the event(s)
that caused the interrupt. The status registers
are RX_PORT_STS1, RX_PORT_STS2, and
CSI_RX_STS.
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