DS90UB964-Q1 Datasheet, PDF (52/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
Bit(s) Field
Type
0
FORCE_REFCLK_D RW
ET
Share 0x03 REV_MASK_ID
Share 0x04 DEVICE_STS
7:4 REVISION_ID
R
3:0 MASK_ID
R
7
CFG_CKSUM_STS R
6
CFG_INIT_DONE
R
Share 0x05
5:0
PAR_ERR_THOLD_ 7:0
HI
RESERVED
R
PAR_ERR_THOLD_ RW
HI
Share 0x06 PAR_ERR_THOLD_L 7:0
O
PAR_ERR_THOLD_L RW
O
Share 0x07 BCC Watchdog
Control
7:1 BCC WATCHDOG RW
TIMER
Share 0x08 I2C Control 1
0
BCC WATCHDOG RW
TIMER DISABLE
7
LOCAL WRITE
RW
DISABLE
6:4 I2C SDA HOLD
RW
3:0 I2C FILTER DEPTH RW
Default Description
0
0x0
0x0
1
1
0x2
0x1
0x0
0x7F
0
0
0x1
0xC
Force indication of external reference clock
0: Normal operation, reference clock detect
circuit indicates the presence of an external
reference clock
1: Force reference clock to be indicated
present
Revision ID
0010: DS90UB964-Q1 A0
0011: DS90UB964-Q1 A1
Mask ID
Config Checksum Passed
This bit is set following initialization if the
Configuration data in the eFuse ROM had a
valid checksum
Power-up initialization complete
This bit is set after Initialization is complete.
Configuration from eFuse ROM has completed.
Reserved
FPD3 Parity Error Threshold High byte
This register provides the 8 most significant
bits of the Parity Error Threshold value. For
each port, if the FPD-Link III receiver detects a
number of parity errors greater than or equal to
this value, the PARITY_ERROR flag is set in
the RX_PORT_STS1 register.
FPD3 Parity Error Threshold Low byte
This register provides the 8 least significant
bits of the Parity Error Threshold value. For
each port, if the FPD-Link III receiver detects a
number of parity errors greater than or equal to
this value, the PARITY_ERROR flag is set in
the RX_PORT_STS1 register.
The watchdog timer allows termination of a
control channel transaction if it fails to
complete within a programmed amount of time.
This field sets the Bi-directional Control
Channel Watchdog Timeout value in units of 2
milliseconds. This field should not be set to 0.
Disable Bi-directional Control Channel
Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
Disable Remote Writes to Local Registers
Setting this bit to a 1 will prevent remote writes
to local device registers from across the control
channel. This prevents writes to the
Deserializer registers from an I2C master
attached to the Serializer. Setting this bit does
not affect remote access to I2C slaves at the
Deserializer.
Internal SDA Hold Time
This field configures the amount of internal
hold time provided for the SDA input relative to
the SCL input. Units are 50 nanoseconds.
I2C Glitch Filter Depth
This field configures the maximum width of
glitch pulses on the SCL and SDA inputs that
is rejected. Units are 5 nanoseconds.
52
Submit Documentation Feedback
Product Folder Links: DS90UB964-Q1
Copyright © 2016, Texas Instruments Incorporated