DS90UB964-Q1 Datasheet, PDF (90/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
Register Maps (continued)
Page Addr
(hex)
Share 0xF9
Register Name
I2C_RX1_ID
Share 0xFA I2C_RX2_ID
Share 0xFB I2C_RX3_ID
Table 12. Serial Control Bus Registers (continued)
Bit(s) Field
Type Default Description
7:1 RX_PORT1_ID
0
RESERVED
7:1 RX_PORT2_ID
0
RESERVED
7:1 RX_PORT3_ID
0
RESERVED
RW
0x0
7-bit Receive Port 1 I2C ID
Configures the decoder for detecting
transactions designated for Receiver port 1
registers. This provides a simpler method of
accessing device registers specifically for port
1 without having to use the paging function to
select the register page. A value of 0 in this
field disables the Port1 decoder.
R
0
Reserved
RW
0x0
7-bit Receive Port 2 I2C ID
Configures the decoder for detecting
transactions designated for Receiver port 2
registers. This provides a simpler method of
accessing device registers specifically for port
2 without having to use the paging function to
select the register page. A value of 0 in this
field disables the Port2 decoder.
R
0
Reserved
RW
0x0
7-bit Receive Port 3 I2C ID
Configures the decoder for detecting
transactions designated for Receiver port 3
registers. This provides a simpler method of
accessing device registers specifically for port
3 without having to use the paging function to
select the register page. A value of 0 in this
field disables the Port3 decoder.
R
0
Reserved
90
Submit Documentation Feedback
Product Folder Links: DS90UB964-Q1
Copyright © 2016, Texas Instruments Incorporated