DS90UB964-Q1 Datasheet, PDF (105/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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11 Layout
DS90UB964-Q1
SNLS500 – JULY 2016
11.1 Layout Guidelines
Circuit board layout and stack-up for the FPD-Link III devices must be designed to provide low-noise power feed
to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback, and interference. Power system performance may be greatly improved
by using thin dielectrics (2 to 4 mils) for power/ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Ceramic capacitors may be in the 2.2-µF to 10-µF range. The voltage rating of the
ceramic capacitors must be at least 5× the power supply voltage being used
TI recommends surface-mount capacitorsdue to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50-µF to 100-µF range, which smooths low frequency switching noise. TI
recommends connectingpower and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body
size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs
Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Differential impedance of 100
Ω are typically recommended for STP interconnect and single-ended impedance of 50 Ω for coaxial interconnect.
The closely coupled lines help to ensure that coupled noise appears as common-mode and thus is rejected by
the receivers. The tightly coupled lines aso radiate less.
11.1.1 CSI-2 Guidelines
1. Route CSI0_D*P/N and CSI1_D*P/N pairs with controlled 100-Ω differential impedance (±20%) or 50-Ω
single-ended impedance (±15%).
2. Keep away from other high-speed signals.
3. Keep length difference between a differential pair to 5 mils of each other.
4. Length matching should be near the location of mismatch.
5. Match trace lengths between pairs to be < 25 mils.
6. Each pair should be separated at least by 3 times the signal trace width.
7. Keep the use of bends in differential traces to a minimum. When bends are used, the number of left and right
bends must be as equal as possible, and the angle of the bend should be ≥ 135 degrees. This arrangement
minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on
EMI.
8. Route all differential pairs on the same layer.
9. Keep the number of VIAS to a minimum — TI recommends keeping the VIA count to 2 or fewer.
10. Keep traces on layers adjacent to ground plane.
11. Do NOT route differential pairs over any plane split.
12. Adding Test points causes impedance discontinuity and therefore negatively impacts signal performance. If
test points are used, place them in series and symmetrically. Test points must not be placed in a manner that
causes a stub on the differential pair.
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