DS90UB964-Q1 Datasheet, PDF (88/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
Register Maps (continued)
Page Addr Register Name
(hex)
RX 0xDA PORT_ISR_HI
RX 0xDB PORT_ISR_LO
Table 12. Serial Control Bus Registers (continued)
Bit(s) Field
Type Default Description
6
IE_LINE_LEN_CHG RW
0
Interrupt on Video Line length
When enabled, an interrupt is generated if the
length of the video line changes. Status is
reported in the LINE_LEN_CHG bit in the
RX_PORT_STS2 register.
5
IE_LINE_CNT_CHG RW
0
Interrupt on Video Line count
When enabled, an interrupt is generated if the
number of video lines per frame changes.
Status is reported in the LINE_CNT_CHG bit in
the RX_PORT_STS2 register.
4
IE_BUFFER_ERR RW
0
Interrupt on Receiver Buffer Error
When enabled, an interrupt is generated if the
Receive Buffer overflow is detected as
reported in the BUFFER_ERROR bit in the
RX_PORT_STS2 register.
3
RESERVED
RW
0
Reserved
2
IE_FPD3_PAR_ERR RW
0
Interrupt on FPD-Link III Receiver Parity Error
When enabled, an interrupt is generated on
detection of parity errors on the FPD-Link III
interface for the receive port. Parity error status
is reported in the PARITY_ERROR bit in the
RX_PORT_STS1 register.
1
IE_PORT_PASS
RW
0
Interrupt on change in Port PASS status
When enabled, an interrupt is generated on a
change in receiver port valid status as reported
in the PORT_PASS bit in the PORT_STS1
register.
0
IE_LOCK_STS
RW
0
Interrupt on change in Lock Status
When enabled, an interrupt is generated on a
change in lock status. Status is reported in the
LOCK_STS_CHG bit in the RX_PORT_STS1
register.
7:3 Reserved
R
0x0
Reserved
2
IS_FPD3_ENC_ERR R
0
FPD-Link III Receiver Encode Error Interrupt
Status
An encoding error on the FPD-Link III interface
for the receive port has been detected. Status
is reported in the FPD3_ENC_ERROR bit in
the RX_PORT_STS2 register.
This interrupt condition is cleared by reading
the RX_PORT_STS2 register.
1
IS_BCC_SEQ_ERR R
0
BCC CRC Sequence Error Interrupt Status
A Sequence Error has been detected for the
Bi-directional Control Channel forward channel
receiver. Status is reported in the
BCC_SEQ_ERROR bit in the
RX_PORT_STS1 register.
This interrupt condition is cleared by reading
the RX_PORT_STS1 register.
0
IS_BCC_CRC_ERR R
0
BCC CRC error detect Interrupt Status
A CRC error has been detected on a Bi-
directional Control Channel frame received
over the FPD-Link III forward channel. Status
is reported in the BCC_CRC_ERROR bit in the
RX_PORT_STS1 register.
This interrupt condition is cleared by reading
the RX_PORT_STS1 register.
7
RESERVED
R
0
Reserved
88
Submit Documentation Feedback
Product Folder Links: DS90UB964-Q1
Copyright © 2016, Texas Instruments Incorporated