DS90UB964-Q1 Datasheet, PDF (30/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
WriteI2C(0xB2,0x83)
WriteI2C(0xB2,0x8D)
WriteI2C(0xB2,0x87)
WriteI2C(0xB2,0x87)
WriteI2C(0xB2,0x83)
WriteI2C(0xB2,0x86)
WriteI2C(0xB2,0x84)
WriteI2C(0xB2,0x86)
WriteI2C(0xB2,0x84)
# TCK Prep
# TCK Zero
# TCK Trail
# TCK Post
# THS Prep
# THS Zero
# THS Trail
# THS Exit
# TLPX
# Set CSI Timing parameters
WriteI2C(0xB0,0x2) # set auto-increment, page 0
WriteI2C(0xB1,0x60) # CSI Port 1
WriteI2C(0xB2,0x83) # TCK Prep
WriteI2C(0xB2,0x8D) # TCK Zero
WriteI2C(0xB2,0x87) # TCK Trail
WriteI2C(0xB2,0x87) # TCK Post
WriteI2C(0xB2,0x83) # THS Prep
WriteI2C(0xB2,0x86) # THS Zero
WriteI2C(0xB2,0x84) # THS Trail
WriteI2C(0xB2,0x86) # THS Exit
WriteI2C(0xB2,0x84) # TLPX
8.4.16 Video Buffers
The DS90UB964-Q1 implements four video line buffer/FIFO, one for each RX channel. The video buffers provide
storage of data payload and forward requirements for sending multiple video streams on the CSI-2 transmit
ports. The total line buffer memory size is a 16-kB block for each RX port.
The CSI-2 transmitter waits for an entire packet to be available before pulling data from the video buffers.
8.4.17 CSI-2 Line Count and Line Length
The DS90UB964-Q1 counts the number of lines (long packets) to determine line count on LINE_COUNT_1/0
registers 0x73–74. For line length, DS90UB964-Q1 generates the word count field in the CSI-2 header on
LINE_LEN_1/0 registers 0x75–0x76.
8.4.18 FrameSync Operation
A frame synchronization signal (FrameSync) can be sent via the back-channel using any of the back channel
GPIOs. The signal can be generated in two different methods. The first option offers sending the external
FrameSync using one of the available GPIO pins on the DS90UB964-Q1 and mapping that GPIO to a back
channel GPIO on one or more of the FPD-Link III ports.
The second option is to have the DS90UB964-Q1 internally generate a FrameSync signal to send via GPIO to
one or more of the attached Serializers.
FrameSync signaling on the four back channels is synchronous. Thus, the FrameSync signal arrives at each of
the four serializers with limited skew.
8.4.18.1 External FrameSync Control
In External FrameSync mode, an external signal is input to the DS90UB964-Q1 via one of the GPIO pins on the
device. The external FrameSync signal may be propagated to one or more of the attached FPD3 Serializers via
a GPIO signal in the back channel.
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