DS90UB964-Q1 Datasheet, PDF (39/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
8.4.19.6 CSI-2 Replicate Mode
In CSI-2 Replicate mode, both ports can be programmed to output the same data. The output from CSI-2 port 0
is also presented on CSI-2 port 1.
To configure this mode of operation, set the CSI_REPLICATE bit in the FWD_CTL2 register (Address 0x21).
8.4.19.7 CSI Transmitter Output Control
Two register controls allow control of CSI Transmitter outputs to disable the CSI Transmitter outputs. If the
OUTPUT_SLEEP_STATE_SELECT (OSS_SEL) control is set to 0 in the GENERAL_CFG 0x02 register, the CSI
Transmitter outputs are forced to the HS-0 state. If the OUTPUT_ENABLE (OEN) register bit is set to 0 in the
GENERAL_CFG register, the CSI pins are set to the high-impedance state.
For normal operation (OSS_SEL and OEN both set to 1), the detection of activity on FPD3 inputs determines the
state of the CSI outputs. The FPD3 inputs are considered active if the Receiver indicates valid lock to the
incoming signal. For a CSI TX port, lock is considered valid if any Received port mapped to the TX port is
indicating Lock.
PDB pin
0
1
1
1
1
Table 9. Table 19. CSI Output Control Options
OSS_SEL
X
0
1
1
1
OEN
X
X
0
1
1
FPD3 INPUT
X
X
X
Inactive
Active
CSI PIN STATE
Hi-Z
HS-0
Hi-Z
Hi-Z
Valid
8.5 Programming
8.5.1 Serial Control Bus
The DS90UB964-Q1 implements two I2C compatible serial control buses. Both I2C ports support local device
configuration and incorporates a bi-directional control channel (BCC) that allows communication with a remote
serializers as well as remote I2C slave devices.
The device address is set via a resistor divider connected to the IDx pin (R1 and R2 – see Figure 33).
VDD18
HOST
SCL
SDA
VDDIO
R1
VR1
IDx
RPU
RPU
R2
DES
SCL
SDA
To other
Devices
Figure 33. Serial Control Bus Connection
The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial
Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For
most applications, TI recommends a 4.7 kΩ pullup resistor to VDDIO. However, the pull-up resistor value may be
adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.
The IDx pin configures the control interface to one of 8 possible device addresses. A pullup resistor and a
pulldown resistor may be used to set the appropriate voltage ratio between the IDx input pin (V_R1) and VDD18,
each ratio corresponding to a specific device address. See Table 10.
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