DS90UB964-Q1 Datasheet, PDF (103/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
10 Power Supply Recommendations
This device provides separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Table 1 provides guidance on which circuit blocks are connected to which power pin pairs. In some
cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
10.1 VDD Power Supply
Each VDD power supply pin must have a 10 nF (or 100 nF) capacitor to ground connected as close as possible
to DS90UB964-Q1 device. TI recommends having additional decoupling capacitors (0.1 µF, 1 µF, and 10 µF) on
i and also recommends having the pins connected to a solid power plane.
10.2 Power-Up Sequencing
The power-up sequence for the DS90UB964-Q1 is as follows:
Table 16. Timing Diagram for the Power-Up Sequence
PARAMETER
T0
VDD11 to VDD18 to VDDIO
T1
VDD11 rise time
T2
VDD11 to VDD18
T3
VDD18 rise time
T4
VDD18 to VDDIO
T5
VDDIO rise time
T6
VDDIO to PDB
T7
PDB pulse width
MIN
TYP
MAX
UNIT
0
ms
0.05
ms
0
ms
0.2
1
ms
0
ms
0.2
1
ms
0
ms
2
ms
NOTES
@10/90%
@10/90%
@10/90%
Hard reset
T0
VDD11
VDD18
T1
T2
VDDIO
T3
T4
T5
T6
PDB
T7
Hard
Reset
REFCLK
Figure 45. Power-Up Sequencing
10.3 PDB Pin
The PDB pin is active HIGH and must remain LOW while the VDD pin power supplies are in transition. An
external RC network on the PDB pin may be connected to ensure PDB arrives after all the supply pins have
settled to the recommended operating voltage. When PDB pin is pulled up to VDD18, a 10-kΩ pullup and a > 10-
μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until both
power supplies have reached steady state.
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