DS90UB964-Q1 Datasheet, PDF (74/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
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Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
RX 0x4E RX_PORT_STS2
Bit(s) Field
Type Default Description
4
LOCK_STS_CHG
R/COR 0
3
BCC_SEQ_ERROR R/COR 0
2
PARITY_ERROR
R
0
1
PORT_PASS
R
0
0
LOCK_STS
R
0
7
LINE_LEN_UNSTAB R/COR 0
LE
6
LINE_LEN_CHG
R/COR 0
5
FPD3_ENCODE_ER R/COR 0
ROR
4
BUFFER_ERROR R/COR 0
3
RESERVED
R
0
Lock Status Changed
This bit is set if a change in receiver lock
status has been detected since the last read of
this register. Current lock status is available in
the LOCK_STS bit of this register
This bit is cleared on read.
Bi-directional Control Channel Sequence Error
Detected
This bit indicates a sequence error has been
detected in the forward control channel. If this
bit is set, an error may have occurred in the
control channel operation. This bit is cleared
on read.
FPD3 parity errors detected
This flag is set when the number of parity
errors detected is greater than the threshold
programmed in the PAR_ERR_THOLD
registers.
1: Number of FPD3 parity errors detected is
greater than the threshold
0: Number of FPD3 parity errors is below the
threshold This bit is cleared when the
RX_PAR_ERR_HI/LO registers are cleared.
Receiver PASS indication This bit indicates the
current status of the Receiver PASS indication.
The requirements for setting the Receiver
PASS indication are controlled by the
PORT_PASS_CTL register.
1: Receive input has met PASS criteria
0: Receive input does not meet PASS criteria
FPD-Link III receiver is locked to incoming data
1: Receiver is locked to incoming data
0: Receiver is not locked
Line Length Unstable
If set, this bit indicates the line length was
detected as unstable during a previous video
frame. The line length is considered to be
stable if all the lines in the video frame have
the same length. This flag will remain set until
read.
Line Length Changed
1: Change of line length detected
0: Change of line length not detected This bit is
cleared on read.
FPD3 Encoder error detected
If set, this flag indicates an error in the FPD-
Link III encoding has been detected by the
FPD-Link III receiver.
This bit is cleared on read.
Note, to detect FP3 Encoder errors, the
LINK_ERROR_COUNT must be enabled with
a LINK_ERR_THRESH value greater than 1.
Otherwise, the loss of Receiver Lock will
prevent detection of the Encoder error.
Packet buffer error detected. If this bit is set,
an overflow condition has occurred on the
packet buffer FIFO.
1: Packet Buffer error detected
0: No Packet Buffer errors detected
This bit is cleared on read.
Reserved
74
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