DS90UB964-Q1 Datasheet, PDF (14/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN OR
FREQUENCY
MIN
CSI-2 TIMING SPECIFICATIONS - GLOBAL OPERATION (Figure 6, Figure 7)
Timeout for receiver to detect
t_CLK-MISS
absence of Clock transitions
and disable the Clock Lane HS-
60
RX ⁽¹⁾
t_CLK-POST
HS exit⁽¹⁾
t_CLK-PRE
t_CLK-
PREPARE
t_CLK-SETTLE
Time HS clock shall be driver
prior to any associated Data
Lane beginning the transition
from LP to HS mode⁽¹⁾
Clock Lane HS Entry⁽¹⁾
Time interval during which the
HS receiver shall ignore any
Clock Lane HS transitions⁽¹⁾
Time-out at Clock Lane Display
t_CLK-TERM-EN Module to enable HS
Termination ⁽¹⁾
60 +
52×UI_IN
ST
CSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI0_CLKP/N
CSI1_CLKP/N
8
38
95
Time
for Dn
to reach
VTERM
-EN
Time that the transmitter drives
t_CLK-TRAIL
the HS-0 state after the last
payload clock bit of a HS
60
transmission burst⁽¹⁾
t_CLK-
PREPARE ⁺
t_CLK-ZERO
TCLK-PREPARE + time that
the transmitter drives the HS-0
state prior to starting the
Clock ⁽¹⁾
300
t_D-TERM-EN
Time for the Data Lane receiver
to enable the HS line
termination ⁽¹⁾
Time
for Dn
to reach
V-
TERM-
EN
Transmitted time interval from
t_EOT
the start of t_HS-TRAIL to the start
of the LP-11 state following a
HS burst⁽¹⁾
t_HS-EXIT
Time that the transmitter drives
LP=11 following a HS burst⁽¹⁾
100
t_HS-PREPARE Data Lane HS Entry⁽¹⁾
t_HS-PREPARE
+ t_HS-ZERO
t_HS-PREPARE + time that the
transmitter drives the HS-0
state prior to transmitting the
Sync sequence⁽¹⁾
40 +
4×UI_INS
T
145 +
10×UI_IN
ST
t_HS-SETTLE
Time interval during which the
HS receiver shall ignore any
Data Lane HS transitions,
starting from the beginning of
t_HS-SETTLE ⁽¹⁾
85 +
6×UI_INS
T
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TYP MAX UNIT
ns
ns
UI_INST
95 ns
300 ns
38 ns
ns
ns
35 +
4×UI_INS ns
T
105 +
12×UI_IN ns
ST
ns
85 +
6×UI_INS ns
T
ns
145 +
10×UI_IN ns
ST
14
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