DS90UB964-Q1 Datasheet, PDF (87/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Page
RX
RX
RX
RX
RX
Addr
(hex)
0xD3
0xD4
0xD5
0xD8
0xD9
Register Name
AEQ_STATUS
ADAPTIVE EQ
BYPASS
AEQ_MIN_MAX
PORT_ICR_HI
PORT_ICR_LO
Table 12. Serial Control Bus Registers (continued)
Bit(s) Field
Type Default Description
4
AEQ_1ST_LOCK_M RW
0
ODE
3
AEQ_RESTART
RW/SC 0
2
SET_AEQ_FLOOR RW
0
1:0 RESERVED
R
0x0
7:6 RESERVED
R
0x0
5:3 EQ_STATUS_1
R
0x0
2:0 EQ_STATUS_2
R
0x0
7:5 EQ STAGE 1
SELECT VALUE
RW
0x3
4
AEQ_LOCK_MODE RW
0
3:1 EQ STAGE 2
SELECT VALUE
0
ADAPTIVE EQ
BYPASS
7:4 AEQ_MAX
RW
0x0
RW
0
RW
0xF
3:0 ADAPTIVE EQ
FLOOR VALUE
RW
0x8
7:2 RESERVED
R
0x0
2
IE_FPD3_ENC_ERR RW
0
1
IE_BCC_SEQ_ERR RW
0
0
IE_BCC_CRC_ERR RW
0
7
RESERVED
RW
0
AEQ First Lock Mode This register bit controls
the Adaptive Equalizer algorithm operation at
initial Receiver Lock.
0 : Initial AEQ lock may occur at any value
1 : Initial Receiver lock will restart AEQ at 0,
providing a more deterministic initial AEQ
value
Set high to restart AEQ adaptation from initial
value. This bit is self clearing. Adaption is
restarted.
AEQ adaptation starts from a pre-set floor
value rather than from zero - good in long
cable situations
Reserved
Reserved
Adaptive EQ Status 1
Adaptive EQ Status 2
EQ select value [5:3] - Used if adaptive EQ is
bypassed.
Adaptive Equalizer lock mode
When set to a 1, Receiver Lock status requires
the Adaptive Equalizer to complete adaption.
When set to a 0, Receiver Lock is based only
on the Lock circuit itself. AEQ may not have
stabilized.
EQ select value [2:0] - Used if adaptive EQ is
bypassed.
1: Disable adaptive EQ
0: Enable adaptive EQ
Adaptive Equalizer Maximum value
This register sets the maximum value for the
Adaptive EQ algorithm.
When AEQ floor is enabled by register
{reg_35[5:4]} the starting setting is given by
this register.
Reserved
Interrupt on FPD-Link III Receiver Encoding
Error
When enabled, an interrupt is generated on
detection of an encoding error on the FPD-Link
III interface for the receive port as reported in
the FPD3_ENC_ERROR bit in the
RX_PORT_STS2 register
Interrupt on BCC SEQ Sequence Error When
enabled, an interrupt is generated if a
Sequence Error is detected for the Bi-
directional Control Channel forward channel
receiver as reported in the BCC_SEQ_ERROR
bit in the RX_PORT_STS1 register.
Interrupt on BCC CRC error detect
When enabled, an interrupt is generated if a
CRC error is detected on a Bi-directional
Control Channel frame received over the FPD-
Link III forward channel as reported in the
BCC_CRC_ERROR bit in the
RX_PORT_STS1 register.
Reserved
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