DS90UB964-Q1 Datasheet, PDF (22/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
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The strapped values can be viewed and/or modified in the following locations:
• Coaxial – Port Configuration COAX_MODE (Register 0x6D[2])
• RX Mode – Port Configuration FPD3_MODE (Register 0x6D[1:0])
8.4.3 REFCLK
A valid 25 MHz (default) reference clock is required on the REFCLK pin 5 for proper operation. REFCLK input
must be continuous. The REFCLK frequency defines all internal clock timers including the back channel rate, I2C
timers, CSI-2 datarate, FrameSync signal parameters, etc. Min stop time (stop at high or stop at low) is 20 uS,
otherwise it is required to reset using PDB. During normal operation if REFCLK input is removed and then re-
applied this may cause CSI-2 output to be disrupted.
The REFCLK LVCMOS input oscillator specifications are listed in Table 3.
PARAMETER
REFERENCE CLOCK
Frequency tolerance
Duty cycle
Rise/Fall Time
Jitter
Frequency
Table 3. REFCLK Oscillator Specifications
TEST CONDITIONS
MIN
10% - 90%
500 kHz - 50 MHz
40%
23
TYP
50%
50
MAX UNIT
±100
60%
8
80
25
ppm
ns
ps p-p
MHz
8.4.4 Input Jitter Tolerance
Input jitter tolerance is the ability of the receiver's CDR PLL to track and recover the incoming serial data stream.
Jitter tolerance at a specific frequency is the maximum jitter permissible before data errors occur. The following
shows the allowable total jitter of the receiver inputs and must be less than the values in the chart.
Amplitude
(UI p-p)
A₁
A₂
g (MHz)
g₁
g₂
Figure 15. Input Jitter Tolerance Plot
INTERFACE
FPD3
Table 4. Input Jitter Tolerance Limit
JITTER AMPLITUDE (UI p-p)
FREQUENCY (MHz) ⁽¹⁾
A1
A2
ƒ1
ƒ2
1
0.4
FPD3_PCLK / 80
FPD3_PCLK / 15
(1) FPD3_PCLK is equivalent to PCLK frequency based on the operating MODE:
10-bit mode: PCLK_Freq. /2
12-bit HF mode: PCLK_Freq. x 2/3
12-bit LF mode: PCLK_Freq.
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