SMJ34020A_06 Datasheet, PDF (91/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
video-interface timing: external sync inputs (see Note 13 and Figure 55)
’34020A-32 ’34020A-40
NO.
MIN MAX MIN MAX
131 tsu(SL-VCKH) Setup time, HSYNC, VSYNC, CSYNC low to VCLK no longer low
20
20
132 tsu(SH-VCKH) Setup time, HSYNC, VSYNC, CSYNC high to VCLK no longer low
20
20
133 th(VCKH-SV) Hold time, HSYNC, VSYNC, CSYNC valid after VCLK high
20
20
NOTE 13: Setup and hold times on asynchronous inputs are required only to assure recognition at indicated clock edges.
UNIT
ns
ns
ns
A
VCLK
B
C
D
HSYNC
VSVNC
CSYNC
(inputs)
133
131
See Note A
133
132
See Note B
NOTES: A. If the falling edge of the sync signal occurs more than th(VCKH-SV) after VCLK edge A and at least tsu(SL-VCKH) before
edge B, the transition is detected at edge B instead of edge A.
B. If the rising edge of the sync signal occurs more than th(VCKH-SV) after VCLK edge C and at least tsu(SH-VCKH) before
edge D, the transition is detected at edge D instead of edge C.
Figure 55. Video-Interface Timing: External Sync Inputs
interrupt timing: LINT1 and LINT2 (see Figure 56)
’34020A-32
’34020A-40
NO.
UNIT
MIN MAX
MIN MAX
Setup time, LINT1 or LINT2 low before LCLK2 no longer
134 tsu(LINTL-CK2H) _low
tQ + 45 ^†
tQ + 40 ^†
ns
135 tw(LINTL)
Pulse duration, LINT1 or LINT2 low
8tQ‡
8tQ‡
ns
† _{Although LINT1 and LINT2 can be asynchronous to the SMJ34020A, this setup ensures recognition of the interrupt on this clock edge.}
‡ _{This pulse duration minimum ensures that the interrupt is recognized by internal logic; however, the level must be maintained until it has been}
acknowledged by the interrupt service routine.
LCLK1
LCLK2
LINT1
LINT2
134
135
Figure 56. Interrupt Timing: LINT1 and LINT2
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
91