SMJ34020A_06 Datasheet, PDF (67/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
signal transition levels (continued)
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
2.6 V
2V
1.5 V
1V
0.6 V
Figure 38. TTL-Level Outputs
TTL-level outputs are driven to a minimum logic-high level of 2.6 V and to a maximum logic-low level of 0.6 V.
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no
longer high is 2 V, and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level
at which the output is said to be no longer low is 1 V, and the level at which the output is said to be high is 2 V.
A V_OL trip level of 1.5 V is used for timing requirements for testing at − 55°C.
test measurement
The test load circuit shown in Figure 39 represents the programmable load of the tester pin electronics that is
used to verify timing parameters of SMJ34020A output signals.
IOL
From Output
Under Test
Test
Point
CLOAD
VLOAD
IOH
Where: IOL = 2 mA (all outputs)
IOH = 400 µA (all outputs)
VLOAD = 1.5 V
CLOAD = 80 pF typical load circuit capacitance
NOTE: The load applied may be set higher than the values
indicated for IOL and IOH during timing tests in order to
reduce signal bounce induced by the tester hardware.
However the timing performance is assured at the stated
load values.
Figure 39. Test Load Circuit
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