SMJ34020A_06 Datasheet, PDF (21/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
dynamic bus sizing on host accesses
If the host makes a read access to a 16-bit wide memory, the SMJ34020A automatically does the second cycle
required to read the rest of the 32-bit word (even if the host did not require a 32-bit cycle). The external logic
must comprehend the sense of SIZE16 or the CAS strobes during the accesses in order to route the data into
the proper external host data transceivers. The SMJ34020A uses the host byte selects HBS0−HBS3 to enable
the CAS strobes when doing a host write.
coprocessor interface
Support for coprocessors is provided through special instructions and bus cycles that allow communication with
the coprocessor. A coprocessor can be register based, depending on the SMJ34020A to do all address
calculations, or it can operate as its own bus controller, using the multiprocessor arbitration scheme. Five basic
cycles are provided for direct communication and control of coprocessors:
D SMJ34020A to coprocessor
D Coprocessor to SMJ34020A
D Move memory to coprocessor
D Move coprocessor to memory
D Coprocessor internal command
The first four of these cycles provide for command of the coprocessor in addition to the movement of parameters
to and from the coprocessor. In this manner, parameters can be sent to the coprocessor and operated upon
without an explicit coprocessor command cycle.
instruction set
The SMJ34020A instruction set can be divided into five categories:
D Graphics instructions
D Coprocessor instructions
D Move instructions
D General-purpose instructions
D Program control and context switching
Specialized graphics instructions manipulate pixel data that is accessed using memory addresses or
XY coordinates. These instructions include graphics operations, such as array and raster operations, pixel
processing, windowing, plane masking, pixel masking, and transparency. Coprocessor instructions allow for the
control and data flow to and from coprocessors that reside in the system. Move instructions comprehend the
bit-addressing and field operations, which manipulate fields of data using linear addressing for transfer to and
from memory and the register file. General-purpose instructions provide a complete set of arithmetic and
Boolean operations on the register file as well as general program control and data processing. Program control
and context switching instructions allow the user to control flow and to save and restore information using
instructions with both register-direct and absolute operands.
clock stretch
The SMJ34020A supports a clock stretching mechanism.
With advances in semiconductor manufacturing, newer versions of the SMJ34020A can be made, each
supporting a higher CLKIN frequency. The increase in CLKIN frequency means that the SMJ34020A machine
cycles execute more quickly, with a consequent increase in code execution speed. However, there comes a
point when, as the machine cycle time becomes shorter, the local-memory control signals begin to violate DRAM
and VRAM timing parameters for certain types of memory access.
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