SMJ34020A_06 Datasheet, PDF (74/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
host-interface-cycle timing requirements (see Note 9 and Figure 43)
34020A-32
34020A-40
NO.
MIN MAX MIN MAX UNIT
23 tsu(AV-CSL)
Setup time, address prior to HCS no longer high
24 th(CSL-AV)
Hold time, address after HCS low
25 tw(CSH)
Pulse duration, HCS high
26 tw(RDH)
Pulse duration, HREAD high
27 tw(WRH)
Pulse duration, HWRITE high
28 tsu(RDH-WRL) Setup time, HREAD high to HWRITE no longer high
29 tsu(WRH-RDL) Setup time, HWRITE high to HREAD no longer high
30 tw(RDL)
Pulse duration, HREAD low
31 tw(WRL)
Pulse duration, HWRITE low
32 tsu(CSL-WRH) Setup time, HCS low to HWRITE no longer low
33 tsu(RDL-CK2L) Setup time, HCS low or HREAD low to LCLK2 no longer high
34
tsu(WRH-CK2L)
Setup time, HWRITE high or HCS high to LCLK2 no longer
high
35 th(CK2L-RDH)
Hold time, HREAD high after LCLK2 no longer high
36 th(CK2L-WRL) Hold time, HWRITE low after LCLK2 no longer high
37
tsu(RDH-CK2L)
Setup time, HREAD high to LCLK2 no longer high, prefetch
read mode
12
12
28
28
28
28
28
18
18
18
30†
30†
0‡
0‡
30†§
10
ns
10
ns
25
ns
25
ns
25
ns
25
ns
25
ns
15
ns
15
ns
15
ns
25†
ns
25†
ns
0‡
ns
0‡
ns
25†§
ns
38 tsu(CSL-RDH)
Setup time, HCS low to HREAD no longer low
18
15
ns
† _{Setup time to ensure recognition of input on this clock edge.}
‡ _{Hold time required to assure response on next clock edge. These values are based on computer simulation and are not tested.}
§ _{When the SMJ34020A is set for block reads, use the deassertion of HREAD to request a local memory cycle at the next sequential address}
location.
NOTE 9: Although HCS, HREAD, and HWRITE can be totally asynchronous to the SMJ34020A, cycle responses to the signals are determined
by local memory cycles.
74
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