SMJ34020A_06 Datasheet, PDF (16/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
reset and DRAM / VRAM initialization (continued)
Just prior to the execution of the first instruction in the reset routine, the SMJ34020A’s internal registers are in
the following states:
D General-purpose register files A and B are uninitialized.
D The ST is set to 0000 0010h.
D The PC contains the most-significant 28 bits of the vector fetched from memory address FFFF FFE0h (the
least significant four bits of the PC are set to zero).
D The BEN bit in the I/O register CONFIG is set to the least significant bit read from the vector fetched from
memory address FFFF FFE0h.
D The CBP, RCM0, and RCM1 bits in the I/O register CONFIG are set to the corresponding bits read from
the vector fetched from memory address FFFF FFE0h. The configuration byte protect bit (CBP) can be set
high to prevent further modification of the lower eight bits of the I/O register CONFIG.
The state of the instruction cache at this time is as follows:
D The SSA (segment start address) registers are uninitialized.
D The LRU (least recently used) stack is set to the initial sequence 0, 1, 2, 3, where 0 occupies the most
recently used position and 3 occupies the least recently used position.
D All P (present) flags are cleared to 0s.
local memory and DRAM/VRAM interface
The SMJ34020A local memory interface consists of an address/data multiplexed bus on which addresses and
data are transmitted. The associated control signals support memory widths of 16 or 32 bits, burst (page-mode)
accesses, local memory-wait states, and optional external data bus buffers. The SMJ34020A DRAM / VRAM
interface consists of an address/address multiplexed bus and the control signals to interface directly to both
DRAMs and VRAMs. The local memory interface and the DRAM / VRAM interface are interrelated and,
therefore, considered together for this description. At the beginning of a typical memory cycle, the address and
status of the current cycle are output on LAD while the ROW address is output on the row/column address (RCA)
bus. See Figure 2. ALTCH and RAS are used to latch the address/status and ROW address, respectively, on
these two buses. LAD is then used to transfer data to or from the memory while the RCA bus is set to the column
address for the memory. (LAD31 is the most significant bit of the address or data).
31
543
0
Address
W
STS
Address — Memory address (select for 128M 32-bit long-words)
W = 0 — Access to lower 16-bit word (even-addressed word or 32-bit boundary)
W = 1 — Access to upper 16-bit word (odd-addressed word)
STS — Bus cycle status code
Figure 2. LAD During the Address Cycle
The address output on the row/column address (RCA) lines is determined by the row/column mode bits (RCM0
and RCM1 in the I/O registers CONFIG) and the state of column-address mode (CAMD) during each memory
cycle (see Table 2). The CAMD is sampled on the internal Q4 clock phase, which allows CAMD to be generated
by static logic wired to the local address/data (LAD) bus.
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