SMJ34020A_06 Datasheet, PDF (12/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
video timing and screen refresh (continued)
HCOUNT register is loaded from SETHCNT by an external HSYNC, VCOUNT is loaded from SETVCNT on an
external VSYNC, and an external CSYNC loads both HCOUNT and VCOUNT from SETHCNT and SETVCNT,
respectively.
The SMJ34020A directly supports VRAMs by generating the serial-data-register transfer cycles necessary to
refresh the display. The memory locations from which the display information is taken, as well as the number
of horizontal scan lines displayed between serial-data-register transfer cycles, are programmable.
The SMJ34020A supports various display resolutions and either interlaced or noninterlaced video. The
SMJ34020A can optionally be programmed to synchronize to externally generated sync signals so that images
created by the SMJ34020A can be superimposed upon images created externally. The external sync mode can
also be used to synchronize the video signals generated by two or more SMJ34020As in a multiple-SMJ34020A
graphics system.
CPU control registers
Five of the I/O registers (CONVDP, CONVMP, CONVSP, CONTROL, and PSIZE) provide CPU control to
configure the SMJ34020A for operation with specific characteristics. These characteristics include pitches for
pixel transfers, window checking mode, Boolean or arithmetic pixel processing operation, transparency mode,
PIXBLT direction control, and pixel size.
interrupt interface registers
Two dedicated I/O registers (INTENB and INTPEND) monitor and mask interrupt requests to the SMJ34020A,
including two externally generated interrupts and three internally generated interrupts. An internal interrupt
request can be generated on one of the following conditions.
D Window violation: an attempt has been made to write a pixel to a location inside or outside a specified
window boundary.
D Host interrupt: the host processor has set the interrupt request bit in the host control register.
D Display interrupt: a specified horizontal line in the frame has been displayed on the screen.
D Bus fault
D Single-step emulator
A nonmaskable interrupt occurs when the host processor sets a control bit in the host interface register (NMI
in HSTCTLH). The host-initiated interrupt is associated with a mode bit (NMIM in HSTCTLH) that enables and
disables saving of the processor state on the stack when the interrupt occurs. This is useful if the host wishes
to use the host interrupt before releasing the SMJ34020A to execute instructions (that is, before the stack
pointer is initialized). A dedicated terminal controls the SMJ34020A reset function.
memory controller/local-memory interface
The memory controller manages the SMJ34020A’s interface to the local memory and automatically performs
the bit alignment and masking necessary to access data located at arbitrary bit boundaries within memory. The
memory controller operates autonomously with respect to the CPU. It has a write queue one field (1 to 32 bits)
deep that permits it to complete those memory cycles necessary to insert a field into memory without delaying
the execution of subsequent instructions. Only when a second memory operation is required before completion
of the first operation is the SMJ34020A forced to defer execution of the subsequent instruction.
The SMJ34020A directly interfaces to standard DRAMs and in particular, to standard video RAMs (VRAMs)
such as the SMJ44C25x multiport VRAMs. The SMJ34020A memory interface consists of the local
address/data bus (LAD), the DRAM row/column address (RCA) bus, and associated control signals. The
currently selected word address (28 bits) and status (4 bits) are multiplexed with data on LAD. The RCA bus
allows direct connection to address/address multiplexed DRAMs from 64K to 16M. Refresh for DRAMs is
supported by CAS-before-RAS (CBR) refresh cycles.
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