SMJ34020A_06 Datasheet, PDF (15/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
reset and DRAM / VRAM initialization
The SMJ34020A drives its RAS signal inactive high as long as RESET remains low. The specifications for
certain DRAM and VRAM devices require that RAS be driven inactive-high for 1 millisecond after power is stable
to provide the proper conditions for the DRAMs. Typically, eight RAS cycles are also required to initialize the
DRAMs for proper operation. In general, holding RESET low for t microseconds ensures that RAS remains high
initially for t−(10t_Q ) microseconds, t_Q being the quarter-cycle time as defined by the input clock period, t_c(CHI).
The SMJ34020A memory controller automatically inserts the required eight RAS cycles after all resets (after
powerup or after the internal reset state) by issuing CAS-before-RAS refresh cycles before it allows the CPU
access to memory. A host must delay requests to memory until the initialization cycles have had sufficient time
to complete. Immediately following reset, the SMJ34020A is set to perform a refresh sequence every eight
cycles.
At times other than powerup, to maintain the memory in DRAMs and do a reset, the RESET pulse must not
exceed the maximum refresh interval of the DRAMs minus the time for the SMJ34020A to refresh the memories.
On reset, the SMJ34020A is set to do a refresh cycle every eight local clock periods. A 30-MHz (CLKIN) system
with one (refresh) bank of D/VRAM would be completely refreshed in one sixteenth of the total memory refresh
interval. The reset pulse then should not exceed about fifteen-sixteenths of the total refresh interval required
by the DRAMs to maintain memory integrity.
If RESET remains low longer than the maximum refresh interval specified for the memory, the previous contents
of the local memory can not be valid after the reset.
initial state following reset
While RESET is asserted low (or while in the internal reset state), the SMJ34020A’s output and bidirectional
pins are forced to the states in Table 1.
Table 1. Initial State of Pins Following a Reset (With GI Low)^†
OUTPUTS DRIVEN HIGH
OUTPUTS DRIVEN LOW
BIDIRECTIONALS DRIVEN TO
HIGH IMPEDANCE
RAS
HRDY
VSYNC
CAS0 −CAS3
CBLNK / VBLNK
HSYNC
WE
DDIN
CSYNC / HBLNK
TR / QE
LAD0 −LAD31
DDOUT
ALTCH
HINT
R0
R1
HOE
HDST
EMU3
RCA0 −RCA12
SF
† _{If GI is high, then all GI-controlled pins are high-impedance. GI-controlled pins are RAS, CAS0 −CAS3, WE, TR / QE, DDOUT, DDIN, ALTCH,}
HOE, HDST, RCA0 −RCA12, LAD0 −LAD31, and SF.
Immediately following reset, all I/O registers are cleared (set to 0000) with the exception of the HLT bit in the
HSTCTLH register. The HLT bit is set to 1 if HCS is high just prior to the low-to-high transition of RESET;
otherwise, it is set to 0.
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