SMJ34020A_06 Datasheet, PDF (53/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
cycle timing examples (continued)
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
HA / HBS
HCS
HREAD
HWRITE
HRDY
DATA
(out)
HOE
Previous Read
Local-Memory Host Read Cycle
Q4
Q1
Q2
Q3
Q4^†
Q1
Q2
Q3
Q4
Q1
1st Read Valid
Local-Memory Host Prefetch Cycle
Q2
Q3
Q4^†
Q1
Q2
Q3
2nd
Q4
Q1
HDST
LAD
GI
1st Address
2nd Address
CAMD
RCA
SF
Row
Column
Row
Column
ALTCH
RAS
CAS
WE
TR / QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
† _{See clock stretch, page 21.}
Figure 28. Back-to-Back Host-Read Cycles With Implicit Addressing; HREAD as Strobe
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