SMJ34020A_06 Datasheet, PDF (18/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
local memory and DRAM/VRAM interface (continued)
Similarly, for each of the other VRAM modes, direct connection is provided for other DRAM modes requiring
larger matrices than the configuration mode. Table 4 gives examples of the connections using this feature.
Table 4. Connections to RCA for CAMD = 1
RCA
64K†
256K†
1M†
12
1M × 32
4M × 32
4M × 32
11
1M × 16
1M × 32
4M × 32
4M × NN
10
256K × 32
1M × 32
1M × NN
4M × 32
4M × NN
9
256K × NN
1M × NN
1M × NN
4M × 32
4M × NN
8
256K × NN
1M × NN
1M × NN
4M × 32
4M × NN
7
256K × NN
1M × NN
1M × NN
4M × 32
4M × NN
6
256K × NN
1M × NN
1M × NN
4M × 32
4M × NN
5
256K × NN
1M × NN
1M × NN
4M × 32
4M × NN
4
256K × NN
1M × NN
1M × NN
4M × 32
4M × NN
3
256K × NN
1M × NN
1M × NN
4M × 32
4M × NN
2
256K × NN
1M × NN
1M × NN
4M × 32
4M × NN
1
256K × 16
1M × 16
1M × 16
4M × 16
0
† _{NN is used for either 16-bit (× 16) or 32-bit (× 32) memory connections.}
4M
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
status codes
Status codes are output on LAD0−LAD3 at the time of the falling edge of ALTCH and can be used to determine
the type of cycle that is being initiated. Table 5 lists the codes and their respective meanings.
Table 5. Status Codes Output on LAD0−LAD3
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
STATUS
Coprocessor code
Emulator operation
Host cycle
DRAM refresh
Video-generated DRAM serial register transfer
CPU-generated VRAM serial register transfer
Write mask load
Color latch load
Data access
Cache fill
Instruction fetch
Interrupt vector fetch
Bus locked operation
Pixel operation
Block write
− RESERVED −
TYPE
OTHER
(00XX)
VRAM
(01XX)
CPU
(1XXX)
18
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