SMJ34020A_06 Datasheet, PDF (57/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
cycle timing examples (continued)
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
HA / HBS
HCS
HREAD
HWRITE
HRDY
(see Note A)
DATA
(in)
DATA
(out)
HOE
1st Write Valid
Previous Read
Valid
Local-Memory Host Write Cycle
Local-Memory Host Prefetch
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1
HDST
LAD
1st Address
2nd Address
GI
CAMD
RCA
Row
Column
Row
Column
SF
ALTCH
RAS
CAS
WE
TR / QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
† _{See clock stretch, page 21.}
NOTE A: HRDY goes high at the start of Q2; however, the memory cycle writing data to memory is not completed
until the start of Q4 when ALTCH, CAS, and HOE return high. The host must not strobe new data into
the external latch until just after the start of Q4.
Figure 30. Host-Write Cycle Back-to-Back With Prefetch of Next Word and Implicit Addressing; HREAD
and HWRITE Used as Strobes
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