SMJ34020A_06 Datasheet, PDF (35/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
Write accesses to 16-bit memory are performed by swapping the data on upper and lower words of LAD and
exchanging data on CAS0 and CAS1 for data on CAS2 and CAS3, respectively (Figure 15). During the first
cycle, data is placed on LAD0−LAD31 as in a normal write. The sampling of SIZE16 low during the first access
indicates that this is 16-bit-wide memory, so the SMJ34020A swaps data on the upper and lower halves of LAD.
Notice that during the first cycle, CAS0 is inactive (because this byte was not selected), and during the second
cycle, CAS2 is inactive due to the exchange of CAS0 for CAS2 and CAS1 for CAS3.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
35