SMJ34020A_06 Datasheet, PDF (45/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
Figure 23 shows the VRAM cycle performed when a horizontal blank reload is requested by the video-control
logic and VCE and SRE in DPYCTL are both set. This cycle is indicated by TR/ QE, WE and SF low and CAS
high at the time RAS goes low. The SOE pin of the VRAMs is used to select between write transfer and
pseudo-write transfer cycles (SOE must be generated by logic external to the SMJ34020A). During the address
portion of the cycle, the status on LAD0 −LAD3 indicates that a video-initiated VRAM register-to-memory
transfer (status code = 0100) is being performed. Although PGMD and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1
GI
LAD
Address
CAMD
RCA
Row
Tap Point
ALTCH
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
Figure 23. Serial-Data-Register-to-Memory-Cycle Timing (VRAM-Write Transfer, Pseudo-Write Transfer)
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