SMJ34020A_06 Datasheet, PDF (24/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
enabling clock stretch (continued)
ADDR
READ
READ
READ
1234123412341234
Stretch Mode Disabled
ADDR
READ
READ
READ
Stretch Mode Enabled
12344123412341234
Stretch
Figure 7. Three 32-Bit Page-Mode Reads
The stretched cycles are designed to accommodate worst-case 32-bit page-mode accesses, so during some
nonpage-mode memory accesses stretches that are not essential can be generated. For example:
ADDR
READ
ADDR
WRITE
1234123412341234
Stretch Mode Disabled
ADDR
READ
ADDR
WRITE
Stretch Mode Enabled
1234412344123441234
Stretch
Stretch
Stretch
Figure 8. One 32-Bit Nonpage-Mode Read-Write
Stretches are inserted in read-modify-write accesses to help ease bus turn-around timings. In the above
example, the second stretch is not needed to help these timings because the read/write turn-around has the
whole of the address cycle to evaluate.
clock-stretch timing example, SMJ34020A-32 and 150-ns DRAMs
This example analyzes a memory interface timing parameter. It shows that the clock-stretch mechanism can
be used to allow the SMJ34020A-32 to avoid a timing violation when interfaced to 100-ns VRAMs.
Consider a system with:
D A SMJ34020A-32,
D A SMJ44C251-10
which has a 32-MHz clock input frequency and hence a 125-ns cycle time, so
t_Q = 31 ns. Timing parameters are taken from this data sheet.
1 megabit × 1 bit DRAM. Timing parameters are taken from the corresponding
Texas Instruments data sheet.
row address hold data after RAS low, t_h(ADV-REL)
Without clock stretch
SMJ4C1024 t_h(RA)
Hold time, row address valid after RAS low
SMJ34020A Parameter 88 Hold time, row address valid after RAS low
Min = 20 ns
Min = t_Q − 5 ns = 26 ns
If RAS is passed through a PAL with a delay of 7 ns, then t_h(RA) seen by the DRAM is 26 ns − 7 ns = 19 ns.
This violates the 20 ns minimum.
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