SMJ34020A_06 Datasheet, PDF (5/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME
TYPE^†
DESCRIPTION
LOCAL MEMORY INTERFACE
ALTCH
O
Address latch. The high-to-low transitions of ALTCH can be used to capture the address and status available on LAD.
A transparent latch (such as a 54ALS373) maintains the current address and status as long as ALTCH remains low.
BUSFLT
Bus fault. External logic asserts BUSFLT high to the SMJ34020A to indicate that an error or fault has occurred on the
current bus cycle. BUSFLT is also used with LRDY to generate externally requested bus cycle retries so that the entire
I
memory address is presented again on LAD.
In the emulation mode, BUSFLT is used for write protecting mapped memory (by disabling CAS outputs for the current
cycle).
DDIN
Data bus direction in enable. DDIN is used to drive the active-high output enables on bidirectional transceivers (such
O as the 54ALS623). The transceivers buffer data input and output on LAD0 −LAD31 when the SMJ34020A is interfaced
to several memories.
DDOUT
O
Data bus direction output enable. DDOUT drives the active-low output enables on bidirectional transceivers (such as
the 54ALS623). The transceivers buffer data input and output on LAD0 −LAD31.
LAD0 −LAD31
32-bit multiplexed local address/data bus. At the beginning of a memory cycle, the word address is output on
I/O LAD4 −LAD31 and the cycle status is output on LAD0 −LAD3. After the address is presented, LAD0 −LAD31 are used
for transferring data within the SMJ34020A system. LAD0 is the LSB and LAD31 is the MSB.
LRDY
Local ready. External circuitry drives LRDY low to inhibit the SMJ34020A from completing a local-memory cycle it has
initiated. While LRDY remains low, the SMJ34020A waits unless the SMJ34020A loses bus priority or is given an
I
external RETRY request (through BUSFLT). Wait states are generated in increments of one full LCLK1 cycle. LRDY can
be driven low to extend local memory-read and memory-write cycles, VRAM serial-data-register-transfer cycles, and
DRAM-refresh cycles. During internal cycles, the SMJ34020A ignores LRDY.
PGMD
Page mode. The memory-decode logic asserts PGMD low if the currently addressed memory supports burst (page
mode) accesses. Burst accesses occur as a series of CAS cycles for a single RAS cycle to memory. LRDY is used with
I
BUSFLT to describe the cycle termination status for a memory cycle.
SIZE16
I
CAMD
I
CAS0 −CAS3
O
RAS
O
RCA0 −RCA12 O
SF
O
TR / QE
O
† _{I = input, O = output}
PGMD is also used in emulation mode for mapping memory.
Bus size. The memory-decode logic can pull SIZE16 low if the currently addressed memory or port supports only 16-bit
transfers. SIZE16 can also be used to determine which 16 bits of the data bus are used for a data transfer.
In the emulation mode, SIZE16 is used to select the size of mapped memory.
DRAM AND VRAM CONTROL
Column-address mode. CAMD dynamically shifts the column address on the RCA0 −RCA12 bus to allow the mixing
of DRAM and VRAM address matrices using the same multiplexed address RCA0 −RCA12 signals.
Four column-address strobes. CAS outputs drive the CAS inputs of DRAMs and VRAMs. CAS0 −CAS3 strobe the
column address on RCA0 −RCA12 to the memory. The four CAS strobes provide byte write-access to the memory.
Row-address strobe. RAS output drives the RAS inputs of DRAMs and VRAMs. RAS strobes the row address on
RCA0 −RCA12 to memory.
Thirteen multiplexed row-address/column-address signals. At the beginning of a memory-access cycle, the row address
for DRAMs is present on RCA0 −RCA12. The row address contains the most significant address bits for the memory.
As the cycle progresses, the memory column address is placed on RCA0 −RCA12. The addresses that are actually
output during row and column times depend on the memory configuration (set by RCM0 and RCM1 in the CONFIG
register) and the state of CAMD during the access. RCA0 is the LSB, and RCA12 is the MSB.
Special function pin. SF is the special-function signal to 1M VRAMs that allows the use of block write, load write mask,
load color mask, and write using write mask. SF is also used to differentiate instructions and addresses for the
coprocessor as part of the coprocessor interface.
Transfer/output-enable. TR / QE drives the TR / QE input of VRAMs. During a local memory-read cycle, TR / QE functions
as an active-low output enable to gate from memory to LAD0 −LAD31. During special VRAM function cycles, TR / QE
controls the type of cycle that is performed.
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