SMJ34020A_06 Datasheet, PDF (64/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
Command Cycle
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLK1
LCLK2
GI
LAD
(TMS34020A)
(see Note A)
CAMD
Command
RCA
ALTCH
(see Note B)
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
(see Note B)
SIZE16
(see Note C)
BUSFLT
R0
R1
NOTES: A. LAD (SMJ34020A): Output to LAD by the SMJ34020A
LAD command:
Coprocessor ID, instruction and status
code present on LAD
B. Although the coprocessor internal command never requires the
use of page mode cycles, PGMD should be held at a valid level
during the start of Q2 after ALTCH has gone low.
C. All coprocessor cycles are implemented as 32-bit operations;
therefore, SIZE16 should be high during these cycles.
Figure 36. Coprocessor-Internal Operation Command Cycle
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