SMJ34020A_06 Datasheet, PDF (78/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
host interface timing responses (write cycle) (see Note 5 and Figure 46)
NO.
PARAMETER
27 tw(WRH)
Pulse duration, HWRITE high
31 tw(WRL)
Pulse duration, HWRITE low
34
tsu(WRH-CK2L)
Setup time, HWRITE high or HCS high to LCLK2 no
longer high
39 td(CK1L-RYH)
46 td(WRL-RYH)
Delay time from LCLK1↑ to HRDY high
Delay time from later of HCS or HWRITE low to HRDY
high (TMS34020 ready)
47 td(WRH-RYL)
Delay time from earlier of HCS or HWRITE high to
HRDY low (end of write)
48 td(CK2L-OEL)
Delay time from LCLK2↓ to HOE low
49 td(CK1_H-OEH) Delay time from LCLK1↓ to HOE high
51 td(RYH-OEH)
Delay time from HRDY↑ to HOE high
† _{Setup time to ensure recognition of input on this clock edge.}
NOTE 5: s = tQ if using the clock stretch;
s = 0 otherwise
34020A-32
MIN
MAX
28
18
30†
tQ + 20
25
25
tQ + 15 + s
tQ + 15
2tQ + 15
34020A-40
UNIT
MIN
MAX
25
ns
15
ns
25†
ns
tQ + 18 ns
20 ns
20 ns
tQ + 13.5 + s ns
tQ + 13.5 ns
2tQ + 13.5 ns
LCLK1
Q4 Q1 Q2 Q3 Q4‡ Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
LCLK2
34
34
31
27
HCS
39
HWRITE
47
47
HRDY
46
HOE
‡ _{See clock stretch, page 21.}
49
48
51
Figure 46. Host-Interface-Cycle Timing Responses (Write-Cycle)
78
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