SMJ34020A_06 Datasheet, PDF (51/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
cycle timing examples (continued)
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
HA / HBS
HCS
HREAD
HWRITE
HRDY
(see Note A)
DATA
(out)
HOE
Previous Read
Valid
Local-Memory Host Read Cycle
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1
HDST
LAD
GI
CAMD
RCA
Row
Column
SF
ALACH
RAS
CAS
WE
TR / QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
† _{See clock stretch, page 21.}
NOTE A: HRDY goes high at the start of Q2; however, data is not strobed into
the external latches until the start of Q4 when HDST goes high.
Figure 27. Host-Read-Cycle Timing (Random/Same Accesses, not From SMJ34020A I/O Registers)
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