SMJ34020A_06 Datasheet, PDF (19/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
dynamic bus sizing
The SMJ34020A supports dynamic bus sizing between 16 and 32 bits on any local memory access. Any
port / memory that is only 16 bits wide must assert SIZE16 low during Q1 (to be valid at the start of Q2) of the
bus cycle accessing the even memory word (LAD4 = 0) corresponding to its address.The SMJ34020A then
performs another memory access to the next 16-bit (odd) word in memory. The SMJ34020A samples SIZE16
at the start of Q2 in the second cycle (access to odd word address) to determine to which half of LAD the port
or memory is aligned. If the port is on LAD0−LAD15, SIZE16 should be low during the second cycle access (odd
word); otherwise, if the port is on LAD16 −LAD31, SIZE16 must be high at this time. The SMJ34020A always
performs two memory cycles to access the 16-bit wide memories, even when attempting only a 16-bit transfer.
The SMJ34020A outputs the four CAS strobes and LAD bus initially aligned for a 32-bit bus. If the memory is
16 bits wide, the two most significant CAS strobes are swapped with the two least significant strobes when it
accesses the second word and the halves of LAD are also swapped; therefore, 16-bit memories need to respond
only to the two CAS strobes corresponding to the upper or lower 16 bits of LAD to which they are connected.
Note that devices connected to LAD0 −LAD15 transfer the least significant word during the first cycle and the
most significant word during the second cycle. Data accesses on LAD16−LAD31 transfer the most significant
word first, then the least significant word.
The second memory cycle forced by SIZE16 is performed as a page mode access if PGMD was low during the
first access. A read-write cycle to the 16-bit page-mode memory requires five bus cycles that occur as address,
read0, read1, write0, write1. If a 16-bit transfer is interrupted due to a bus fault, the restart causes the entire
access to be restarted.
For memory that supports page-mode accesses (PGMD low), SIZE16 is sampled during each access to
memory. If SIZE16 is high on the even word access, then a 32-bit transfer occurs over LAD0−LAD31. If SIZE16
is low on the even word access (16-bit wide memory), then it is sampled again on the odd word access to
determine to which half of LAD the memory is connected (low for connection to LAD0 −LAD15 or high for
connection to LAD16 −LAD31).
special 1-M VRAM cycles
The SMJ34020A provides control for special function VRAM cycles that are available in the 1-M devices. These
cycles are obtained by the appropriate timing control of SF, CAS, TR/ QE, and WE of the VRAMs at the falling
edge of RAS. The cycles include:
D Load write mask
D Load color mask
D Block write (no mask)
D Block write (current mask)
D Write using mask
D Alternate write transfer
In addition, other special modes can be implemented by using external logic.
multiprocessor arbitration
The multiprocessor interface allows multiple processors to operate in a system sharing the same local memory.
The use of the bus grant in GI and the priority request signals R0 and R1 allows a flexible method of passing
control from one processor to another. The control scheme allows local memory cycles to occur back-to-back,
even when passing control from one SMJ34020A to another. Synchronization of multiple SMJ34020As in a
system occurs at reset with the rising edge of RESET meeting the setup and hold requirements to CLKIN, so
all SMJ34020As are certain to respond to RESET during the same quarter cycle. RESET is not required to be
synchronous to CLKIN except to allow synchronization of multiple SMJ34020As in a system.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
19